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freescale semiconductor technical data ? 2011, 2012, 2014 freescale semiconductor, inc. all rights reserved. this document provides an overview of the mpc 8309 powerquicc ii pro processor features . the MPC8309 is a cost-effective, highly integrated communications processor that addresses the requireme nts of several networking applications including residential gatewa ys, modem/routers, industrial control, and test and measurement applications. the MPC8309 extends current powerquicc offerings, adding higher cpu performance, additional functionality, and faster interfaces, while addressing the requirements related to time-to-market, pr ice, power consumption, and board real estate. this docum ent describes the electrical characteristics of MPC8309. to locate published errata or upda tes for this document, refer to the MPC8309 product summar y page on our website listed on the back cover of this document or contact your local freescale sales office. document number:MPC8309ec rev. 3, 04/2014 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 7 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 4. clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. ddr2 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7. enhanced local bus . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. ethernet and mii management . . . . . . . . . . . . . . . . . 22 9. tdm/si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10. hdlc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12. usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14. esdhc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 15. flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 17. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 18. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 19. ipic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 20. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 21. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 22. package and pin listings . . . . . . . . . . . . . . . . . . . . . . 52 23. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 24. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 25. system design information . . . . . . . . . . . . . . . . . . . . 75 26. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 78 27. document revision history . . . . . . . . . . . . . . . . . . . . 80 MPC8309 powerquicc ii pro integrated communications processor family hardware specifications
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 2 freescale semiconductor overview 1 overview the MPC8309 incorporates the e300c3 (mpc603e-based ) core built on power ar chitecture? technology, which includes 16 kb of each l1 instruction and data caches, dual integer units, and on-chip memory management units (mmus). the mp c8309 also includes a 32-bit pci controller, two dma engines and a 16/32-bit ddr2 memory controller with 8-bit ecc. a new communications complex based on quicc engi ne technology forms the heart of the networking capability of the MPC8309. the quicc engine block contains several pe ripheral controllers and a 32-bit risc controller. protocol suppor t is provided by the main workhor ses of the device?the unified communication controllers (uccs). a block diagram of the MPC8309 is shown in the following figure. figure 1. MPC8309 block diagram each of the five uccs ca n support a variety of comm unication protocols such as 10/100 mbps mii/rmii ethernet, hdlc and tdm. in summary, the MPC8309 provides users with a highly integrated, fully programmable communications processor. this helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standa rds and evolving system requirements. 2 rmii/mii 2x tdm ports 16-kb d-cache 16-kb i-cache e300c3 core with power 2x duart interrupt i2c timers gpio enhanced ddr2 controller controller baud rate generators accelerators single 32-bit risc cp serial dma serial interface quicc engine? block ucc7 ucc5 ucc3 ucc2 ucc1 time slot assigner 16 kb multi-user ram fpu management spi rtc local bus 2x hdlc 1 rmii/mii 2x ieee 1588 usb 2.0 hs host/device/otg ulpi 4 flexcan esdhc 48 kb instruction ram dma engine 2 dma engine 1 pci controller io sequencer
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 3 overview 1.1 features the major features of the device are as follows: ? e300c3 power architecture processor core ? enhanced version of the mpc603e core ? high-performance, superscalar processor core with a four-sta ge pipeline and low interrupt latency times ? floating-point, dual integer units, load/store, system register, and branch processing units ? 16-kb instruction cache and 16-kb da ta cache with lockable capabilities ? dynamic power management ? enhanced hardware program debug features ? software-compatible with freescale proces sor families implemen ting power architecture technology ? separate pll that is clocked by the system bus clock ? performance monitor ? quicc engine block ? 32-bit risc controller for flexible support of the communications peripherals with the following features: ? one clock per instruction ? separate pll for operating frequency that is independent of system?s bus and e300 core frequency for power and performance optimization ? 32-bit instruction object code ? executes code from internal iram ? 32-bit arithmetic logi c unit (alu) data path ? modular architecture allowing for easy functional enhancements ? slave bus for cpu access of regi sters and multiuser ram space ? 48 kb of instruction ram ? 16 kb of multiuser data ram ? serial dma channel for receive and transmit on all se rial channels ? five unified communication controllers (ucc s) supporting the following protocols and interfaces: ? 10/100 mbps ethernet/ieee std. 802.3? through mii and rm ii interfaces. ? ieee std. 1588? support ? hdlc/transparent (bit rate up to quicc engine operating frequency / 8) ? hdlc bus (bit rate up to 10 mbps) ? asynchronous hdlc (bit rate up to 2 mbps) ? two tdm interfaces supporting up to 128 quicc multichannel controller channels, each running at 64 kbps
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 4 freescale semiconductor overview for more information on quicc engine sub-modules, see quicc engine block reference manual with protocol interworking . ? ddr sdram memory controller ? programmable timing supporting ddr2 sdram ? integrated sdram clock generation ? supports 8-bit ecc ? 16/32-bit data interface, up to 333-mhz data rate ? 14 address lines ? the following sdram configurations are supported: ? up to two physical banks (chip selects), 512-mb addressable sp ace for 32 bit data interface ? 64-mbit to 2-gbit devices with x8/ x16/x32 data ports (no direct x4 support) ? one 16-bit device or two 8-bit devices on a 16- bit bus, or two 16-bit devices or four 8-bit devices on a 32-bit bus support for up to 16 simultaneous open pages for ddr2 ? two clock pair to support up to 4 dram devices ? supports auto refresh ? on-the-fly power management using cke ? enhanced local bus controller (elbc) ? multiplexed 26-bit addr ess and 8-/16-bit data operating at up to 66 mhz ? eight chip selects supporting eight external slaves ? four chip selects dedicated ? four chip selects offered as multiplexed option ? supports boot from parallel nor flash and parallel nand flash ? supports programmable clock ratio dividers ? up to eight-beat burst transfers ? 16- and 8-bit ports, separate lwe for each 8 bit ? three protocol engines availabl e on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user programmable machines (upms) ? nand flash control machine (fcm) ? variable memory block sizes for fcm, gpcm, and upm mode ? default boot rom chip select with configurable bus width (8 or 16) ? provides two write enable signals to allow si ngle byte write access to external 16-bit elbc slave devices ? integrated programmable in terrupt controller (ipic) ? functional and programming compatibility with the mpc8260 interrupt controller ? support for external and intern al discrete interrupt sources ? programmable highest priority request ? six groups of interrupts with programmable priority
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 5 overview ? external and internal interrupt s directed to host processor ? unique vector number fo r each interrupt source ?pci interface ? designed to comply with pci local bus specification, revision 2.3 ? 32-bit pci interface operating at up to 66 mhz ? pci 3.3-v compatible ? not 5-v compatible ? support for host and agent modes ? support for pci-to-memory a nd memory-to-pci streaming ? memory pre-fetching of pci read accesses and support for delayed read transactions ? support for posting of processor-to -pci and pci-to-memory writes ? on-chip arbitration, supporting three masters on pci ? arbiter support for two-level prio rity request/grant signal pairs ? support for accesses to all pci address spaces ? support for parity ? selectable hardware-enforced coherency ? address translation units for addres s mapping between hos t and peripheral ? mapping from an external 32-/64-bit addre ss space to the internal 32-bit local space ? support for dual address cycle (dac) (as a target only) ? internal configuration regi sters accessible from pci ? selectable snooping for inbound transactions ? four outbound translation address windows ? support for mapping 32-bit internal local memory space to an external 32-bit pci address space and translating that address within the pci space ? four inbound translation address window s corresponding to defined pci bars ? the first bar is 32-bits and dedi cated to on-chip register access ? the second bar is 32-bits for general use ? the remaining two bars may be 32- or 64-bits and are al so for general use ? enhanced secure digita l host controller (esdhc) ? compatible with the sd host controller standa rd specification version 2.0 with test event register support ? compatible with the mmc system specification version 4.2 ? compatible with the sd memory card specification version 2.0 and supports the high capacity sd memory card ? compatible with the sd input/output (sdio) card specification, version 2.0 ? designed to work with sd memory, mini sd memory, sdio, minisdio, sd combo, mmc, mmc plus , and rs-mmc cards ? card bus clock frequency up to 33.33 mhz.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 6 freescale semiconductor overview ? supports 1-/4-bit sd and sd io modes, 1-/4-bit modes ? up to 133 mbps data transfer for sd/sdi o/mmc cards using 4 pa rallel data lines ? supports block sizes of 1 ~ 4096 bytes ? universal serial bus (u sb) dual-role controller ? designed to comply with universal serial bus r evision 2.0 specification ? supports operation as a stand-alone usb host controller ? supports operation as a stand-alone usb device ? supports high-speed (480-mbps), full-speed (12-mbps), and lo w-speed (1.5-mbps) operations. low speed is only supported in host mode. ? flexcan module ? full implementation of the can pr otocol specification version 2.0b ? up to 64 flexible message buffers of zero to eight bytes data length ? powerful rx fifo id filtering, capable of matching incoming ids ? selectable backwards compatibility wi th previous flexcan module version ? programmable loop-back mode supporting self-test operation ? global network time, synchr onized by a specific message ? independent of the transm ission medium (an external transceiver is required) ? short latency time due to an arbitration scheme for high-priority messages ? dual i 2 c interfaces ? two-wire interface ? multiple-master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ?i 2 c1 can be used as the boot sequencer ? dma engine1 ? support for the dma e ngine with the following features: ? sixteen dma channels ? all data movement vi a dual-address transfers: read fr om source, write to destination ? transfer control descriptor (t cd) organized to support two-d eep, nested transfer operations ? channel activation via one of two methods (for both the methods , one activation per execution of the minor loop is required): ? explicit software initiation ? initiation via a channel-to-channel li nking mechanism for continuous transfers (independent channel linki ng at end of minor loop and/or major loop) ? support for fixed-priority and round-robin channel arbitration ? channel completion reported vi a optional interrupt requests ? support for scatter/ga ther dma processing ? io sequencer
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 7 electrical characteristics ? direct memory access (dma) controller (dma engine 2) ? four independent fully pr ogrammable dma channels ? concurrent execution across multiple channels with pr ogrammable bandwidth control ? misaligned transfer capability for source/destination address ? data chaining and direct mode ? interrupt on completed segment, error, and chain ? duart ? supports 2 duart ? each has two 2-wire interfaces (rxd, txd) ? the same can be configured as one 4-wire interface (rxd, txd, rts, cts) ? programming model compat ible with the origin al 16450 uart and the pc16550d ? serial peripheral interface (spi) ? master or slave support ? power management controller (pmc) ? supports core doze/nap/sleep/ power management ? exits low power state and re turns to full-on mode when ? the core internal time base unit i nvokes a request to exit low power state ? the power management contro ller detects that the system is not idle and there are outstanding transactions on the intern al bus or an external interrupt. ? parallel i/o ? general-purpose i/o (gpio) ? 56 parallel i/o pins multiple xed on various chip interfaces ? interrupt capability ? system timers ? periodic interrupt timer ? software watchdog timer ? eight general-purpose timers ? real time clock (rtc) module ? maintains a one-second count, unique over a period of thousands of years ? two possible clock sources: ? external rtc clock (rtc_pit_clk) ? csb bus clock ? ieee std. 1149.1? compliant jtag boundary scan 2 electrical characteristics this section provides the ac and dc electrical sp ecifications and thermal characteristics for the MPC8309. the MPC8309 is currently targeted to these sp ecifications. some of th ese specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 8 freescale semiconductor electrical characteristics 2.1 overall dc electrical characteristics this section covers the ratings, c onditions, and other characteristics. 2.1.1 absolute maximum ratings the following table provides th e absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.26 v ? pll supply voltage av dd1 av dd2 av dd3 ?0.3 to 1.26 v ? ddr2 dram i/o voltage gv dd ?0.3 to 1.98 v ? pci, local bus, duart, system control and power management, i 2 c, spi, mii, rmii, mii management, esdhc, flexcan, usb and jtag i/o voltage ov dd ?0.3 to 3.6 v 2 input voltage ddr2 dram signals mv in ?0.3 to (gv dd +0.3) v 3 ddr2 dram reference mv ref ?0.3 to (gv dd +0.3) v 3 local bus, duart, sys_clk_in, system control and power management, i 2 c, spi, and jtag signals ov in ?0.3 to (ov dd +0.3) v 4 pci ov in ?0.3 to (ov dd + 0.3) v storage temperature range t stg ?55to150 c? notes: 1. functional and tested operating conditions are given in ta b l e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresse s beyond those listed may affect device reliability or cause permanent damage to the device. 2. ovdd here refers to nvdda, nvddb, nvddc, nvddf, nvddg, and nvddh from the ball map. 3. caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 4. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 9 electrical characteristics 2.1.2 power supply voltage specification the following table provides the recommended opera ting conditions for the MPC8309. note that these values are the recommended and tested operating conditions. proper device ope ration outside of these conditions is not guaranteed. the following figure shows the undershoot and overs hoot voltages at the interfaces of the MPC8309 figure 2. overshoot/undershoot voltage for gv dd /ov dd table 2. recommended operating conditions characteristic symbol recommended value unit note core supply voltage v dd 1.0v50mv v 1 pll supply voltage av dd1 av dd2 av dd3 1.0v50mv v 1 ddr2 dram i/o voltage gv dd 1.8 v 100 mv v 1 pci, local bus, duart, system control and power management, i 2 c, spi, mii, rmii, mii management, esdhc, flexcan,usb and jtag i/o voltage ov dd 3.3 v 300 mv v 1, 3 junction temperature t a /t j 0to105 c2 notes: 1. gv dd , ov dd , av dd , and v dd must track each other and must vary in the same direction?either in the positive or negative direction. 2. minimum temperature is specified with t a (ambient temperature); maximum temperature is specified with t j (junction temperature). 3. ovdd here refers to nvdda, nvddb, nvddc, nvddf, nvddg, and nvddh from the ball map. gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/ov dd + 20% g/ov dd g/ov dd + 5% of t interface 1 1. t interface refers to the clock period associated with the bus clock interface. v ih v il note:
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 10 freescale semiconductor electrical characteristics 2.1.3 output driver characteristics the following table provides information on the ch aracteristics of the output driver strengths. 2.1.4 input capacitance specification the following table describes the input capaci tance for the sys_clk_in pin in the MPC8309. 2.2 power sequencing the device does not require the core supply voltage (v dd ) and i/o supply voltages (gv dd and ov dd ) to be applied in any particular order. note that during power ramp-up, be fore the power supplies are stable and if the i/o voltages are supplied before the core volta ge, there might be a period of time that all input and output pins are actively driven and cause contention and excessive cu rrent. in order to avoid actively driving the i/o pins and to eliminate excessive current draw, apply the core voltage (v dd ) before the i/o voltage (gv dd and ov dd ) and assert poreset before the power supplies fully ramp up. in the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the i/o supplies reach 0.7 v; see figure 3 . once both the power supplies (i/o voltage and core voltage) are stable, wait for a minimum of 32 cl ock cycles before negating poreset . note there is no specific pow er down sequence requireme nt for the device. i/o voltage supplies (gv dd and ov dd ) do not have any ordering requirements with respect to one another. table 3. output drive capability driver type output impedance ( ) supply voltage (v) local bus interface utilities signals 42 ov dd =3.3 pci signal 25 ddr2 signal 18 gv dd =1.8 duart, system control, i2c, spi, jtag 42 ov dd =3.3 gpio signals 42 ov dd =3.3 table 4. input capacitance specification parameter/condition symbol min max unit note input capacitance for all pi ns except sys_clk_in and qe_clk_in c i 68pf? input capacitance for sys_clk_in and qe_clk_in c iclk_in 10 ? pf 1 note: 1. the external clock generator should be able to drive 10 pf.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 11 power characteristics figure 3. mpc 8309 power-up sequencing example 3 power characteristics the typical power dissipation for this family of MPC8309 devices is shown in the following table. table 5. MPC8309 power dissipation core frequency (mhz) quicc engine frequency (mhz) csb frequency (mhz) typical maximum unit note 266 233 133 0.341 0.920 w 1, 2, 3 333 233 133 0.361 0.938 w 1, 2, 3 400 233 133 0.381 0.969 w 1,2,3 417 233 167 0.429 1.003 w 1,2,3 notes: 1. the values do not include i/o supply power (ov dd and gv dd ), but it does include v dd and av dd power. for i/o power values, see ta b l e 6 . 2. typical power is based on a nominal voltage of v dd = 1.0 v, ambient temperature, and the core running a dhrystone benchmark application. the measurements were take n on the evaluation board using wc process silicon. 3. maximum power is based on a voltage of v dd = 1.05 v, wc process, a junction t j = 105 c, and a smoke test code. t 90% v core voltage (v dd ) i/o voltage (gv dd and ov dd ) 0 0.7 v poreset >= 32 t sys_clk_in / pci_sync_in
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 12 freescale semiconductor clock input timing the following table shows the estimated t ypical i/o power dissipation for the device. 4 clock input timing this section provides the clock input dc and ac electrical characteristics for the MPC8309. note the rise/fall time on qu icc engine input pins s hould not exceed 5 ns. this should be enforced especially on cloc k signals. rise time refers to signal transitions from 10% to 90% of ov dd ; fall time refers to transitions from 90% to 10% of ov dd . 4.1 dc electrical characteristics the following table provides the clock input (sys_c lk_in/pci_sync_in) dc specifications for the MPC8309. these specifications are also applicable for qe_clk_in. table 6. typical i/o power dissipation interface parameter gv dd (1.8 v) ov dd (3.3 v) unit comments ddr i/o 65% utilization 1.8 v r s = 20 r t = 50 1 pair of clocks 266 mhz, 1 16 bits 0.149 ?w ? local bus i/o load = 25 pf 1 pair of clocks 66 mhz, 26 bits ?0.415w 1 quicc engine block and other i/os tdm serial, hdlc/tran serial, duart, mii, rmii, ethernet management, usb, pci, spi, timer output, flexcan, esdhc note: 1. typical i/o power is based on a nominal voltage of v dd = 3.3v, ambient temperature, and the core running a dhrystone benchmark application. the measurements were tak en on the evaluation board using wc process silicon. table 7. sys_clk_in dc electrical characteristics parameter condition symbol min max unit input high voltage ? v ih 2.4 ov dd +0.3 v input low voltage ? v il ?0.3 0.4 v sys_clk_in input current 0 v v in ov dd i in ?5 a sys_clk_in input current 0 v v in 0.5 v or ov dd ? 0.5 v v in ov dd i in ?5 a sys_clk_in input current 0.5 v v in ov dd ? 0.5 v i in ?50 a
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 13 reset initialization 4.2 ac electrical characteristics the primary clock source for the MPC8309 can be one of two inputs, sys_clk_in or pci_sync_in, depending on whether the device is configured in pci host or agent mode. the following table provides the clock input (sys_clk_in/pci_sync_in) ac timing specifications for the MPC8309. these specifications are also a pplicable for qe_clk_in. 5 reset initialization this section describes the ac electrical specifications for the reset initialization timing requirements of the MPC8309. the following table provid es the reset initializa tion ac timing specifications for the reset component(s). table 8. sys_clk_in ac timing specifications parameter/condition symbol min typical max unit note sys_clk_in frequency f sys_clk_in 24 ? 66.67 mhz 1 sys_clk_in cycle time t sys_clk_in 15 ? 41.6 ns ? sys_clk_in rise and fall time t kh , t kl 1.1 ? 2.8 ns 2 pci_sync_in rise and fall time t pch , t pcl 1.1 ? 2.8 ns 2 sys_clk_in duty cycle t khk /t sys_clk_ in 40 ? 60 % 3 sys_clk_in jitter ? ? ? 150 ps 4, 5 notes: 1. caution: the system, core and quicc engine block must not exceed their respective maximum or minimum operating frequencies. 2. rise and fall times for sys_clk_in are measured at 0.33 and 2.97 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. the sys_clk_in driver?s closed loop jitter bandwidth shou ld be < 500 khz at ?20 db. the bandwidth must be set low to allow cascade-connected pll-bas ed devices to track sys_clk_in dr ivers with the s pecified jitter. 6. spread spectrum is allowed up to 1% down-spread @ 33khz (max rate). table 9. reset initialization timing specifications parameter/condition min max unit note required assertion time of hreset to activate reset flow 32 ? t sys_clk_in 1 required assertion time of poreset with stable cl ock applied to sys_clk_in or pci_sync_in (in agent mode) 32 ? t sys_clk_in 1 hreset assertion (output) 512 ? t sys_clk_in 1
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 14 freescale semiconductor ddr2 sdram the following table provides the pll lock times. 5.1 reset signals dc electrical characteristics the following table provides the dc electrical characteristics for the MPC8309 reset signals mentioned in table 9 . 6ddr2 sdram this section describes the dc and ac electrical specifications for the ddr2 sdram interface of the MPC8309. note that ddr2 sdram is gv dd (typ) = 1.8 v. 6.1 ddr2 sdram dc electrical characteristics the following table provides the recommended operating conditions for the ddr2 sdram component(s) of the MPC8309 when gv dd (typ) = 1.8 v . the following table provides th e ddr2 capacitance when gv dd (typ) = 1.8 v. input setup time for por configuration signals (cfg_reset_source[0:3]) with re spect to negation of poreset 4?t sys_clk_in 1, 2 input hold time for por config signals with respect to negation of hreset 0 ? ns 1, 2 notes: 1. t sys_clk_in is the clock period of t he input clock app lied to sys_clk_in. for more details, see the mpc 8309 powerquicc ii pro integrated communications processor family reference manual . 2. por configuration signals cons ist of cfg_reset_source[0:3]. table 10. pll lock times parameter/condition min max unit note pll lock times ? 100 s? table 11. reset signals dc electrical characteristics characteristic symbol condition min max unit note output high voltage v oh i oh = ?6.0 ma 2.4 ? v 1 output low voltage v ol i ol = 6.0 ma ? 0.5 v 1 output low voltage v ol i ol = 3.2 ma ? 0.4 v 1 input high voltage v ih ?2.0ov dd +0.3 v 1 input low voltage v il ??0.30.8v? input current i in 0 v v in ov dd ? 5 a? note: 1. this specification applies when operating from 3.3 v supply. table 9. reset initialization timing specifications (continued)
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 15 ddr2 sdram 6.2 ddr2 sdram ac electrical characteristics this section provides the ac electrical char acteristics for the ddr2 sdram interface. 6.2.1 ddr2 sdram input ac timing specifications this table provides the input ac timing specifications for the ddr2 sdram (gv dd (typ) = 1.8 v). the following table provides the input ac timing specifications for the ddr2 sdram interface. table 12. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v parameter/condition symbol min max unit note i/o supply voltage gv dd 1.7 1.9 v 1 i/o reference voltage mvref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mvref ? 0.04 mvref + 0.04 v 3 input high voltage v ih mvref+ 0.125 gv dd +0.3 v ? input low voltage v il ?0.3 mvref ? 0.125 v ? output leakage current i oz ?9.9 9.9 a4 output high current (v out = 1.35 v) i oh ?13.4 ? ma ? output low current (v out = 0.280 v) i ol 13.4 ? ma ? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mvref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mvref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mvref. this rail should track variations in the dc level of mvref. 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 13. ddr2 sdram capacitance for gv dd (typ) = 1.8 v parameter/condition symbol min max unit note input/output capacitance: dq, dqs c io 68pf1 delta input/output ca pacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 1.8 v 0.100 v, f = 1 mhz, t a =25c, v out = gv dd 2, v out (peak-to-peak) = 0.2 v. table 14. ddr2 sdram input ac timing specifications for 1.8-v interface at recommended operating conditions with gv dd of 1.8 v 100mv. parameter symbol min max unit note ac input low voltage v il ? mvref ? 0.25 v ? ac input high voltage v ih mvref + 0.25 ? v ?
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 16 freescale semiconductor ddr2 sdram the following figure shows the input timing diagram for the ddr controller. figure 4. ddr input timing diagram 6.2.2 ddr2 sdram output ac timing specifications the following table provides the output ac timing specifications for the ddr2 sdram interfaces. table 15. ddr2 sdram input ac timing specifications at recommended operating conditions with gv dd of 1.8v 100mv. parameter symbol min max unit note controller skew for mdqs?mdq/mdm t ciskew ps 1, 2 266 mhz ?750 750 notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that is captured with mdqs[n]. this should be su btracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew . this can be determined by the equation: t diskew = (t/4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew . table 16. ddr2 sdram output ac timing specifications at recommended operating conditions with gv dd of 1.8v 100mv. parameter symbol 1 min max unit note mck cycle time, (mck/mck crossing) t mck 5.988 8 ns 2 addr/cmd output setup with respect to mck t ddkhas ns 3 333 mhz 266 mhz 2.4 2.5 ? addr/cmd output hold with respect to mck t ddkhax ns 3 333 mhz 266 mhz 2.4 2.5 ? mck [n] mck[n] t mck mdq[x] mdqs[n] t diskew d1 d0 t diskew
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 17 ddr2 sdram mcs output setup with respect to mck t ddkhcs ns 3 333 mhz 266 mhz 2.4 2.5 ? mcs output hold with respect to mck t ddkhcx ns 3 333 mhz 266 mhz 2.4 2.5 ? mck to mdqs skew t ddkhmh ?0.6 0.6 ns 4 mdq/mdm output setup with respect to mdqs t ddkhds, t ddklds ns 5 333 mhz 266 mhz 0.8 0.9 ? mdq/mdm output hold with respect to mdqs t ddkhdx, t ddkldx ps 5 333 mhz 266 mhz 900 1100 ? mdqs preamble start t ddkhmp 0.75 x t mck ?ns6 mdqs epilogue end t ddkhme 0.4 x t mck 0.6 x t mck ns 6 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram ou tput signals except mck/mck , mcs , and mdq/mdm/mdqs. for the addr/cmd setup and hold specifications, it is assum ed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck(n) clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 register. this is typically set to the same delay as the clock adjusts in the clk_cntl register. the timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the MPC8309 powerquicc ii pro integrated communications processor family reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data stro be (mdqs) and any corresponding bit of data (mdq), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. t ddkhmp follows the symbol conventions described in note 1. table 16. ddr2 sdram output ac ti ming specifications (continued) at recommended operating conditions with gv dd of 1.8v 100mv. parameter symbol 1 min max unit note
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 18 freescale semiconductor ddr2 sdram the following figure shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 5. timing diagram for t ddkhmh the following figure shows the dd r2 sdram output timing diagram. figure 6. ddr2 sdram output timing diagram mdqs mck mck t mck mdqs t ddkhmh (max) = 0.6 ns t ddkhmh (min) = ?0.6 ns addr/cmd t ddkhas ,t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x]/ mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddkhme t ddkhmp mecc[x]
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 19 enhanced local bus 7 enhanced local bus this section describes the dc and ac electrical speci fications for the enhanced local bus interface of the MPC8309. 7.1 enhanced local bus dc electrical characteristics the following table provides the dc electrical characteristics for th e enhanced local bus interface. 7.2 enhanced local bus ac electrical specifications the following table describes the general timing parameters of the enhanced local bus interface of MPC8309. table 17. enhanced local bus dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd +0.3 v low-level input voltage v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ?0.2 ? v low-level output voltage, i ol =100 av ol ?0.2v input current i in ?5 a table 18. enhanced local bus general timing parameters parameter symbol 1 min max unit note local bus cycle time t lbk 15 ? ns 2 input setup to loca l bus clock (lclk n )t lbivkh 7 ? ns 3, 4 input hold from local bus clock (lclk n )t lbixkh 1.0 ? ns 3, 4 local bus clock (lclk n ) to output valid t lbkhov ?3ns3 local bus clock (lclk n ) to output high impedance for lad/ldp t lbkhoz ?4ns5 lale output fall to lad output transition (latch hold time) t lbotot 3?ns? lale output rise to lclk negative edge t lalehov ?3ns? lale output fall to lclk negative edge t laletot ?5.0 ? ns ? notes : 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go inva lid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). 2. all timings are in reference to falling edge of lclk0 (for all outputs and for lgta and lupwait inputs) or rising edge of lclk0 (for all other inputs). 3. all signals are measured from ov dd /2 of the rising/falling edge of lclk0 to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing meas urements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or eq ual to the leakage current specification.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 20 freescale semiconductor enhanced local bus the following figure provides the ac test load for the local bus. figure 7. enhanced local bus ac test load the following figures show the local bus signals. these figures have been given indicate timing parameters only and do not reflect actu al functional operation of interface. figure 8. enhanced local bus signals output z 0 = 50 ov dd /2 r l = 50 output signals: lbctl/lbcke/loe t lbkhov t lbkhov lclk[n] input signals: lad[0:15] output signals: lad[0:15] t lbixkh t lbivkh t lbkhoz t lbotot lale input signal: lgta t lbixkh t lbivkh t lbixkh t laletot t lalehov
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 21 enhanced local bus figure 9. enhanced local bus signals, gpcm/upm signals for lcrr[clkdiv] = 2 lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 input signals: lad[0:15]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:1]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 22 freescale semiconductor ethernet and mii management figure 10. enhanced local bus signals, gpcm/upm si gnals for lcrr[clkdiv] = 4 8 ethernet and mii management this section provides the ac and dc electrica l characteristics for ethernet interfaces. 8.1 ethernet controller (10/100 mbps)?mii/rmii electrical characteristics the electrical characteristics speci fied here apply to all mii (media independent interface) and rmii (reduced media independent in terface), except mdio (management data input/output) and mdc (management data clock). th e mii and rmii are defined for 3.3 v. th e electrical characte ristics for mdio and mdc are specified in section 8.3, ?ethernet management in terface electrical characteristics . ? 8.1.1 dc electrical characteristics all mii and rmii drivers and receivers comply with the dc parametric attributes specified in the following table. lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 upm mode output signals: lcs [0:3]/lbs [0:1]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz t2 t4 input signals: lad[0:15]
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 23 ethernet and mii management 8.2 mii and rmii ac timing specifications the ac timing specifications for mii and rmii are presented in this section. 8.2.1 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 8.2.1.1 mii transmit ac timing specifications the following table provides the mii transmit ac timing specifications. table 19. mii and rmii dc electrical characteristics parameter symbol conditions min max unit supply voltage 3.3 v ov dd ?33.6v output high voltage v oh i oh = ?4.0 ma ov dd =min 2.40 ov dd +0.3 v output low voltage v ol i ol =4.0 ma ov dd = min gnd 0.50 v input high voltage v ih ??2.0ov dd +0.3 v input low voltage v il ? ? ?0.3 0.90 v input current i in 0 v v in ov dd ?5 a table 20. mii transmit ac timing specifications at recommended operating conditions with ov dd of 3.3 v 300mv. parameter/condition symbol 1 min typical max unit tx_clk clock period 10 mbps t mtx ?400?ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh /t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise v il (min) to v ih (max) t mtxr 1.0 ? 4.0 ns tx_clk data clock fall v ih (max) to v il (min) t mtxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outp uts (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to th ree letters representing the cloc k of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall ti mes, the latter convention is used with the appropriate letter: r (rise) or f (fall).
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 24 freescale semiconductor ethernet and mii management the following figure provides the ac test load. figure 11. ac test load the following figure shows the mi i transmit ac timing diagram. figure 12. mii transmit ac timing diagram 8.2.1.2 mii receive ac timing specifications the following table provides the mii receive ac timing specifications. table 21. mii receive ac timing specifications at recommended operating conditions with ov dd of 3.3 v 300mv. parameter/condition symbol 1 min typical max unit rx_clk clock period 10 mbps t mrx ?400?ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise v il (min) to v ih (max) t mrxr 1.0 ? 4.0 ns rx_clk clock fall time v ih (max) to v il (min) t mrxf 1.0 ? 4.0 ns note: 1. the symbols used for timing spec ifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signa ls (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to th e time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three le tters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for ri se and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). output z 0 = 50 ov dd /2 r l = 50 tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 25 ethernet and mii management the following figure shows the mii receive ac timing diagram. figure 13. mii receive ac timing diagram 8.2.2 rmii ac timing specifications this section describes the rmii transm it and receive ac timing specifications. 8.2.2.1 rmii transmit ac timing specifications the following table provides the rmii transmit ac timing specifications. the following figure provides the ac test load. figure 14. ac test load table 22. rmii transmit ac timing specifications at recommended operating conditions with ov dd of 3.3 v 300mv. parameter/condition symbol 1 min typical max unit ref_clk clock t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % ref_clk to rmii data txd[1:0], tx_en delay t rmtkhdx 2 ? 13 ns ref_clk data clock rise v il (min) to v ih (max) t rmxr 1.0 ? 4.0 ns ref_clk data clock fall v ih (max) to v il (min) t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t rmtkhdx symbolizes rmii transmit timing (rmt) for the time t rmx clock reference (k) going high (h) until data ou tputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t rmx represents the rmii(rm) reference (x) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data output z 0 = 50 ov dd /2 r l = 50
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 26 freescale semiconductor ethernet and mii management the following figure shows the rm ii transmit ac timing diagram. figure 15. rmii transmit ac timing diagram 8.2.2.2 rmii receive ac timing specifications the following table provides the rmii receive ac timing specifications. table 23. rmii receive ac timing specifications at recommended operating conditions with ov dd of 3.3 v 300mv. parameter/condition symbol 1 min typical max unit ref_clk clock period t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % rxd[1:0], crs_dv, rx_er setup time to ref_clk t rmrdvkh 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk t rmrdxkh 2.0 ? ? ns ref_clk clock rise v il (min) to v ih (max) t rmxr 1.0 ? 4.0 ns ref_clk clock fall time v ih (max) to v il (min) t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing spec ifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t rmrdvkh symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) reach the valid state (v) relative to the t rmx clock reference (k) going to the high (h) state or setup time. also, t rmrdxkl symbolizes rmii receive ti ming (rmr) with respect to the time data input signals (d) went invalid (x) relative to the t rmx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particul ar functional. for example, the subscript of t rmx represents the rmii (rm) reference (x) cl ock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). ref_clk txd[1:0] t rmtkhdx t rmx t rmxh t rmxr t rmxf tx_en
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 27 ethernet and mii management the following figure shows the rm ii receive ac timing diagram. figure 16. rmii receive ac timing diagram 8.3 ethernet management interface electrical characteristics the electrical characteristics sp ecified here apply to mii mana gement interface signals mdio (management data input/output) and mdc (management data clock). th e electrical characteristics for mii, and rmii are specified in section 8.1, ?ethernet controller ( 10/100 mbps)?mii/rm ii electrical characteristics.? 8.3.1 mii management dc electrical characteristics mdc and mdio are defined to operate at a supply voltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in the following table. 8.3.2 mii management ac electrical specifications the following table provides the mii ma nagement ac timing specifications. table 24. mii management dc electrical characteristics when powered at 3.3 v parameter symbol conditions min max unit supply voltage (3.3 v) ov dd ?33.6v output high voltage v oh i oh = ?1.0 ma ov dd =min 2.40 ov dd + 0.3 v output low voltage v ol i ol =1.0ma ov dd = min gnd 0.50 v input high voltage v ih ?2.00?v input low voltage v il ? ? 0.80 v input current i in 0 v v in ov dd ?5 a table 25. mii management ac timing specifications at recommended operating conditions with ov dd is 3.3 v 300mv. parameter/condition symbol 1 min typical max unit note mdc frequency f mdc ?2.5?mhz? mdc period t mdc ?400?ns? mdc clock pulse width high t mdch 32 ? ? ns ? ref_clk rxd[1:0] t rmrdxkh t rmx t rmxh t rmxr t rmxf crs_dv rx_er t rmrdvkh valid data
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 28 freescale semiconductor ethernet and mii management the following figure shows the mi i management ac timing diagram. figure 17. mii management interface timing diagram 8.3.3 ieee 1588 dc specifications the ieee 1588 dc timing sp ecifications are given in the following table. mdc to mdio delay t mdkhdx 10 ? 70 ns ? mdio to mdc setup time t mddvkh 8.5 ? ? ns ? mdio to mdc hold time t mddxkh 0??ns? mdc rise time t mdcr ? ? 10 ns ? mdc fall time t mdhf ? ? 10 ns ? note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 26. ieee 1588 dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = -8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2ma ? 0.4 v table 25. mii management ac timing specifications (continued) at recommended operating conditions with ov dd is 3.3 v 300mv. parameter/condition symbol 1 min typical max unit note mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 29 ethernet and mii management 8.3.4 ieee 1588 ac specifications the ieee 1588 ac timing sp ecifications are given in the following table. input high voltage v ih ? 2.0 ov dd + 0.3 v input low voltage v il ? - 0.3 0.8 v input current i in 0v v in ov dd ? 5 a table 27. ieee 1588 ac timing specifications at recommended operating conditions with ov dd of 3.3 v 300mv. parameter/condition symbol min typ max unit note qe_1588_clk clock period t t1588clk 2.5 ? t rx_clk 9ns 1, 3 qe_1588_clk duty cycle t t1588clkh /t t1588clk 40 50 60 % ? qe_1588_clk peak-to-peak jitter t t1588clkinj ??250ps? rise time qe_1588_clk (20%?80%) t t1588clkinr 1.0 ? 2.0 ns ? fall time qe_1588_clk (80%?20%) t t1588clkinf 1.0 ? 2.0 ns ? qe_1588_clk_out clock period t t1588clkout 2 t t1588clk ??ns? qe_1588_clk_out duty cycle t t1588clkoth /t t1588clkout 30 50 70 % ? qe _1588_pulse_out t t1588ov 0.5 ? 3.0 ns ? qe _1588_trig_in pulse width t t1588trigh 2 t t1588clk_max ??ns2 notes: 1.t rx_clk is the max clock period of quicc engine receiving clock selected by tmr_ctrl[cksel]. see the MPC8309 powerquicc ii pro integrated communications processor reference manual, for a description of tmr_ctrl registers. 2. it needs to be at least two times of clock per iod of clock selected by tmr_ctrl[cksel]. see the MPC8309 powerquicc ii pro integrated communications processor reference manual, for a description of tmr_ctrl registers. 3. the maximum value of t t1588clk is not only defined by the value of t rx_clk , but also defined by the recovered clock. for example, for 10/100 mbps modes, the maximum value of t t1588clk is 3600 and 280ns, respectively. table 26. ieee 1588 dc electrical characteristics characteristic symbol condition min max unit
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 30 freescale semiconductor ethernet and mii management the following figure provides the data and command output timing diagram. figure 18. ieee1588 output ac timing the following figure provides the data and command input timing diagram. figure 19. ieee1588 input ac timing fec_1588_clk_out fec_1588_pulse_out fec_1588_trig_out t t1588ov t t1588clkout t t1588clkouth note: the output delay is count starting rising edge if t t1588clkout is non-inverting. otherwise, it is count starting falling edge. fec_1588_clk fec_1588_trig_in t t1588trigh t t1588clk t t1588clkh
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 31 tdm/si 9tdm/si this section describes the dc and ac electrical speci fications for the time-divisi on-multiplexed and serial interface of the MPC8309. 9.1 tdm/si dc electrical characteristics the following table provides the dc electri cal characteristics for the MPC8309 tdm/si. 9.2 tdm/si ac timing specifications the following table provides the tdm/si i nput and output ac timing specifications. the following figure provides the ac test load for the tdm/si. figure 20. tdm/si ac test load table 28. tdm/si dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in 0 v v in ov dd ?5 a table 29. tdm/si ac timing specifications 1 characteristic symbol 2 min max unit tdm/si outputs?external clock delay t sekhov 214ns tdm/si outputs?external clock high impedance t sekhox 210ns tdm/si inputs?external clock input setup time t seivkh 5?ns tdm/si inputs?external clock input hold time t seixkh 2?ns notes: 1. output specifications are measured from the 50% level of the rising edge of qe_clk_in to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t sekhox symbolizes the tdm/si outputs external timing (se) for the time t tdm/si memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). output z 0 = 50 ov dd /2 r l = 50
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 32 freescale semiconductor hdlc the following figure represents the ac timing from table 29 . note that although the specifications generally reference the risi ng edge of the clock, these ac timing diag rams also apply when the falling edge is the active edge. figure 21. tdm/si ac timing (external clock) diagram 10 hdlc this section describes the dc and ac electrical speci fications for the high leve l data link control (hdlc), of the MPC8309. 10.1 hdlc dc electrical characteristics the following table provides the dc electrical characteristics for the MPC8309 hdlc protocol. 10.2 hdlc ac timing specifications the following table provides the input and output ac timing specificati ons for hdlc protocol. table 30. hdlc dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in 0 v v in ov dd ? 5 a table 31. hdlc ac timing specifications 1 characteristic symbol 2 min max unit outputs?internal clock delay t hikhov 09ns outputs?external clock delay t hekhov 1 12 ns outputs?internal clock high impedance t hikhox 05.5ns tdm/siclk (input) t seixkh t seivkh t sekhov input signals: tdm/si (see note) output signals: tdm/si (see note) note: the clock edge is selectable on tdm/si. t sekhox
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 33 hdlc the following figure provides the ac test load. figure 22. ac test load figure 23 and figure 24 represent the ac timing from table 31 . note that although the specifications generally reference the risi ng edge of the clock, these ac timing diag rams also apply when the falling edge is the active edge. the following figure shows the timing with external clock. figure 23. ac timing (external clock) diagram outputs?external clock high impedance t hekhox 18ns inputs?internal clock input setup time t hiivkh 9?ns inputs?external clock input setup time t heivkh 4?ns inputs?internal clock input hold time t hiixkh 0?ns inputs?external clock input hold time t heixkh 1?ns notes: 1. output specifications are measured from the 50% level of the rising edge of qe_clk_in to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 31. hdlc ac timing specifications 1 (continued) characteristic symbol 2 min max unit output z 0 = 50 ov dd /2 r l = 50 serial clk (input) t heixkh t heivkh t hekhov input signals: (see note) output signals: (see note) note: the clock edge is selectable. t hekhox
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 34 freescale semiconductor pci the following figure shows the timing with internal clock. figure 24. ac timing (internal clock) diagram 11 pci this section describes the dc a nd ac electrical specifications for the pci bus of the MPC8309. 11.1 pci dc electrical characteristics table 32 provides the dc electrical characteris tics for the pci interface of the MPC8309. 11.2 pci ac electrical specifications this section describes the general ac timing parameters of the pci bus of the MPC8309. note that the pci_clk or pci_sync_in signal is used as the pci input clock de pending on whether the MPC8309 is configured as a host or agent device. table 33 shows the pci ac timing sp ecifications at 66 mhz. . table 34 shows the pci ac timing specifications at 33 mhz. table 32. pci dc electrical characteristics 1,2 parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 2 ov dd + 0.3 v low-level input voltage v il v out v ol (max) ?0.3 0.8 v high-level output voltage v oh ov dd = min, i oh = ?100 a ov dd ? 0.2 ? v low-level output voltage v ol ov dd = min, i ol = 100 a ?0.2v input current i in 0 v v in ov dd ? 5 a notes: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta bl e 2 . 2. ranges listed do not meet the full ra nge of the dc specifications of the pci 2.3 local bus specifications. serial clk (output) t hiixkh t hikhov input signals: (see note) output signals: (see note) t hiivkh t hikhox note: the clock edge is selectable.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 35 pci figure 25 provides the ac test load for pci. figure 25. pci ac test load table 33. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?6.0ns2 output hold from clock t pckhox 1?ns2 clock to output high impedance t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0 ? ns 2, 4 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional bl ock)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the inpu t signals (i) reach the vali d state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.3 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are m easured at the pin. table 34. pci ac timing specifications at 33 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?11ns2 output hold from clock t pckhox 2?ns2 clock to output high impedance t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0 ? ns 2, 4 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional bl ock)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the inpu t signals (i) reach the vali d state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.3 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin. output z 0 = 50 ov dd /2 r l = 50
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 36 freescale semiconductor usb figure 26 shows the pci input ac timing conditions. figure 26. pci input ac timing measurement conditions figure 27 shows the pci output ac timing conditions. figure 27. pci output ac timing measurement condition 12 usb 12.1 usb controller this section provides the ac and dc electrica l specifications for the usb (ulpi) interface. 12.1.1 usb dc electrical characteristics the following table provides the dc electri cal characteristics for the usb interface. 12.1.2 usb ac electrical specifications the following table describe s the general timing paramete rs of the usb interface. table 35. usb dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2.0 ov dd +0.3 v low-level input voltage v il ?0.3 0.8 v input current i in ?5 a high-level output voltage, i oh = ?100 av oh ov dd ?0.2 ? v low-level output voltage, i ol = 100 av ol ?0.2v t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output t pckhox
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 37 usb the following figures provide the ac test load and signals for the usb, respectively. figure 28. usb ac test load figure 29. usb signals table 36. usb general timing parameters parameter symbol 1 min max unit note usb clock cycle time t usck 15 ? ns ? input setup to usb clock?all inputs t usivkh 4?ns? input hold to usb clock?all inputs t usixkh 1?ns? usb clock to output valid?all outputs (except usbdr_stp_usbdr_stp) t uskhov ?7ns? usb clock to output valid?usbdr_stp t uskhov ?7.5ns? output hold from usb clock?all outputs t uskhox 2?ns? note : 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t usixkh symbolizes usb timing (usb) for the input (i) to go invalid (x ) with respect to the time the usb clock reference (k) goes high (h). also, t uskhox symbolizes us timing (usb) for the usb clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. output z 0 = 50 ov dd /2 r l = 50 output signals t uskhov usbdr_clk input signals t usixkh t usivkh t uskhox
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 38 freescale semiconductor duart 13 duart this section describes the dc and ac electrical specifications for the duart interface of the MPC8309. 13.1 duart dc electrical characteristics the following table provides the dc electrical characteristics for the duart interface of the MPC8309. 13.2 duart ac electrical specifications the following table provides the ac timing para meters for the duart interface of the MPC8309. table 37. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd +0.3 v low-level input voltage ov dd v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ?0.2 ? v low-level output voltage, i ol = 100 av ol ?0.2v input current (0 v v in ov dd ) 1 i in ?5 a note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta bl e 2 . table 38. duart ac timing specifications parameter value unit note minimum baud rate 256 baud ? maximum baud rate >1,000,000 baud 1 oversample rate 16 ? 2 notes: 1. actual attainable baud rate is limited by the latency of interrupt processing. 2. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 39 esdhc 14 esdhc this section describes the dc and ac electrical specifications for the esdhc interface of the device. 14.1 esdhc dc electrical characteristics the following table provides th e dc electrical characteristi cs for the esdhc interface. 14.2 esdhc ac timing specifications the following table provides the esdhc ac timing specifications as defined in figure 30 and figure 31 . table 39. esdhc interface dc electrical characteristics at recommended operating conditions with ov dd =3.3v characteristic symbol condition min max unit note input high voltage v ih ?0.625 ov dd ?v1 input low voltage v il ? ? 0.25 ov dd v1 output high voltage v oh i oh = ?100 a at ov dd min 0.75 ov dd ?v? output low voltage v ol i ol =100 a at ov dd min ? 0.125 ov dd v? output high voltage v oh i oh = ?100 ma ov dd ?0.2 ? v 2 output low voltage v ol i ol =2ma ? 0.3 v 2 input/output leakage current i in /i oz ??1010 a? notes: 1. note that the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 2 . . 2. open drain mode for mmc cards only. table 40. esdhc ac timing specifications at recommended operating conditions with ov dd =3.3v parameter symbol 1 min max unit notes sd_clk clock frequency: sd/sdio full-speed/high-speed mode mmc full-speed/high-speed mode f shsck 0 25/33.25 20/52 mhz 2, 4 sd_clk clock low time?full-speed/high-speed mode t shsckl 10/7 ? ns 4 sd_clk clock high time?full-speed/high-speed mode t shsckh 10/7 ? ns 4 sd_clk clock rise and fall times t shsckr/ t shsckf ?3ns4 input setup times: sd_cmd, sd_datx, sd_cd to sd_clk t shsivkh 5?ns4
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 40 freescale semiconductor esdhc the following figure provides the esdhc clock input timing diagram. figure 30. esdhc clock input timing diagram the following figure provides the data and command input/output timing diagram. figure 31. esdhc data and command input/output timing diagram referenced to clock input hold times: sd_cmd, sd_datx, sd_cd to sd_clk t shsixkh 2.5 ? ns 3, 4 output delay time: sd_clk to sd_cmd, sd_datx valid t shskhov ?3 3 ns 4 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first three letters of functional block)(signal)(state) (reference)(state) for inputs and t (first three letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t fhskhov symbolizes esdhc high-speed mode device timing (shs) clock refere nce (k) going to the high (h) state, with respect to the output (o) reaching the invalid state (x) or output hold time. note that in general , the clock reference symbol is based on fiv e letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. in full-speed mode, the clock frequency value can be 0?25 mhz for an sd/sdio card and 0?20 mhz for an mmc card. in high-speed mode, the clock frequency value can be 0?33.25 mhz for an sd/sdio card and 0?52 mhz for an mmc card. 3. to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 4. c card 10 pf, (1 card), and c l = c bus + c host +c card 40 pf table 40. esdhc ac timing specifications (continued) at recommended operating conditions with ov dd =3.3v parameter symbol 1 min max unit notes esdhc t shsckr external clock vm vm vm t shsck t shsckf vm = midpoint voltage (ov dd /2) operational mode t shsckl t shsckh vm = midpoint voltage (ov dd /2) sd_ck external clock sd_dat/cmd vm vm vm vm inputs sd_dat/cmd outputs t shsivkh t shsixkh t shskhov
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 41 flexcan 15 flexcan this section describes the dc and ac electrical specifications for the flexcan interface. 15.1 flexcan dc electrical characteristics the following table provides th e dc electrical characteristi cs for the flexcan interface . 15.2 flexcan ac timing specifications the following table provides the ac timing specifications for the flexcan interface. table 41. flexcan dc electrical characteristics (3.3v) for recommended operating conditions, see ta bl e 2 parameter symbol min max unit notes input high voltage v ih 2?v 1 input low voltage v il ?0.8 v 1 input current (ov in = 0 v or ov in = ov dd )i in ?5 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0.4 v ? note: 1. min v il and max v ih values are based on the respective min and max ov in values found in ta bl e 2 . 2. ov in represents the input voltage of the supply. it is referenced in ta bl e 2 . table 42. flexcan ac timing specifications for recommended operating conditions, see ta bl e 2 parameter min max unit notes baud rate 10 1000 kbps ?
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 42 freescale semiconductor i 2 c 16 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the MPC8309. 16.1 i 2 c dc electrical characteristics the following table provides the dc electrical characteristics for the i 2 c interface of the MPC8309. 16.2 i 2 c ac electrical specifications the following table provides the ac timing parameters for the i 2 c interface of the MPC8309. table 43. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 300mv. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd +0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.4v1 output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 c b 250 ns 2 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns3 capacitance for each i/o pin c i ?10pf? input current (0 v v in ov dd )i in ?5 a4 notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. c b = capacitance of one bus line in pf. 3. refer to the mpc 8309 powerquicc ii pro integrated communications processor family reference manual for information on the digital filter used. 4. i/o pins obstructs the sda and scl lines if ov dd is switched off. table 44. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see ta bl e 4 3 ). parameter symbol 1 min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl 1.3 ? s high period of the scl clock t i2ch 0.6 ? s setup time for a repeated start condition t i2svkh 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s data setup time t i2dvkh 100 ? ns data hold time: i 2 c bus devices t i2dxkl 300 0.9 3 s rise time of both sda and scl signals t i2cr 20 + 0.1 c b 4 300 ns
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 43 i 2 c the following figure provides the ac test load for the i 2 c. figure 32. i 2 c ac test load the following figure shows the ac timing diagram for the i 2 c bus. figure 33. i 2 c bus ac timing diagram fall time of both sda and scl signals t i2cf 20 + 0.1 c b 4 300 ns setup time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d ) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the st op condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2. MPC8309 provides a hold time of at least 300 ns for the sda signal (referred to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkl has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. table 44. i 2 c ac electrical specifications (continued) all values refer to v ih (min) and v il (max) levels (see ta bl e 4 3 ). parameter symbol 1 min max unit output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 44 freescale semiconductor timers 17 timers this section describes the dc a nd ac electrical specifications for the timers of the MPC8309. 17.1 timer dc electrical characteristics the following table provides the dc electrical characteristics for the MPC8309 timer pins, including tin, tout , tgate , and rtc_pit_clk. 17.2 timer ac timing specifications the following table provides the timer i nput and output ac timing specifications. the following figure provides the ac test load for the timers. figure 34. timers ac test load table 45. timer dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh =?6.0ma 2.4 ? v output low voltage v ol i ol =6.0ma ? 0.5 v output low voltage v ol i ol =3.2ma ? 0.4 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in 0 v v in ov dd ? 5 a table 46. timer input ac timing specifications 1 characteristic symbol 2 min unit timers inputs?minimum pulse width t tiwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of sys_clk_in. timings are measured at the pin. 2. timer inputs and outputs are asynchronous to any visible clock. timer outputs should be synchronized before use by any external synchronous logic. timer inputs are required to be valid for at least t tiwid ns to ensure proper operation. output z 0 = 50 ov dd /2 r l = 50
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 45 gpio 18 gpio this section describes the dc and ac electric al specifications for the gpio of the MPC8309. 18.1 gpio dc electrical characteristics the following table provides the dc electri cal characteristics for the MPC8309 gpio. 18.2 gpio ac timing specifications the following table provides the gpio i nput and output ac timing specifications. the following figure provides the ac test load for the gpio. figure 35. gpio ac test load table 47. gpio dc electrical characteristics characteristic symbol con dition min max unit notes output high voltage v oh i oh = ?6.0 ma 2.4 ? v 1 output low voltage v ol i ol = 6.0 ma ? 0.5 v 1 output low voltage v ol i ol = 3.2 ma ? 0.4 v 1 input high voltage v ih ?2.0ov dd +0.3 v 1 input low voltage v il ??0.30.8v? input current i in 0 v v in ov dd ? 5 a? note: 1. this specification applies w hen operating from 3.3-v supply. table 48. gpio input ac timing specifications 1 characteristic symbol 2 min unit gpio inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of sys_clk_in. timings are measured at the pin. 2. gpio inputs and outputs are asynchronous to any visible clock. gpio outputs should be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid ns to ensure proper operation. output z 0 = 50 ov dd /2 r l = 50
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 46 freescale semiconductor ipic 19 ipic this section describes the dc and ac electrical specifications for the external interrupt pins of the MPC8309. 19.1 ipic dc electrical characteristics the following table provides the dc electrical characteristics for the external interrupt pins of the MPC8309. 19.2 ipic ac timing specifications the following table provides the ipic i nput and output ac ti ming specifications. 20 spi this section describes the dc and ac electric al specifications for the spi of the MPC8309. 20.1 spi dc electrical characteristics the following table provides the dc elect rical characteristics for the MPC8309 spi. table 49. ipic dc electrical characteristics 1,2 characteristic symbol condition min max unit input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in ??5 a output high voltage v oh i ol = -8.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applies for pins irq , mcp_out , and qe ports interrupts. 2. mcp_out is open drain pins, thus v oh is not relevant for those pins. table 50. ipic input ac timing specifications 1 characteristic symbol 2 min unit ipic inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of sys_clk_in. timings are measured at the pin. 2. ipic inputs and outputs are asynchronous to any visible cl ock. ipic outputs should be synchronized before use by any external synchronous logic. ipic inputs are required to be valid for at least t piwid ns to ensure proper operation when working in edge triggered mode.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 47 spi 20.2 spi ac timing specifications the following table and provide the spi i nput and output ac ti ming specifications. the following figure provides the ac test load for the spi. figure 36. spi ac test load figure 37 and figure 38 represent the ac timing from table 52 . note that although the specifications generally reference the risi ng edge of the clock, these ac timing diag rams also apply when the falling edge is the active edge. table 51. spi dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in 0 v v in ov dd ? 5 a table 52. spi ac timing specifications 1 characteristic symbol 2 min max unit spi outputs?master mode (internal clock) delay t nikhov 0.5 6 ns spi outputs?slave mode (external clock) delay t nekhov 28ns spi inputs?master mode (interna l clock) input setup time t niivkh 6?ns spi inputs?master mode (internal clock) input hold time t niixkh 0?ns spi inputs?slave mode (external clock) input setup time t neivkh 4?ns spi inputs?slave mode (external clock) input hold time t neixkh 2?ns notes: 1. output specifications ar e measured from the 50% level of the rising edge of spiclk to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t nikhov symbolizes the nmsi outputs internal timing (ni) for the time t spi memory clock reference (k) goes from the high state (h) until outputs (o) are valid (v). 3. all units of output delay must be enabled for 8309_output_port spimosi_lpgl0(spi master mode) 4. delay units must not be enabled for slave mode. output z 0 = 50 ov dd /2 r l = 50
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 48 freescale semiconductor jtag the following figure shows the spi timi ng in slave mode (external clock). figure 37. spi ac timing in slave mode (external clock) diagram the following figure shows the spi timi ng in master mode (internal clock). figure 38. spi ac timing in master mode (internal clock) diagram 21 jtag this section describes the dc a nd ac electrical specifications for the ieee std. 1149.1? (jtag) interface of the MPC8309. 21.1 jtag dc electrical characteristics the following table provides the dc electrical characteristics for th e ieee std. 1149.1 (jtag) interface of the MPC8309. table 53. jtag interface dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh =?6.0ma 2.4 ? v output low voltage v ol i ol =6.0ma ? 0.5 v output low voltage v ol i ol =3.2ma ? 0.4 v spiclk (input) t neixkh t neivkh t nekhov input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 49 jtag 21.2 jtag ac electrical characteristics this section describes the ac el ectrical specifications for the ieee std. 1149.1 (jtag) interface of the MPC8309. the following table provides the jtag ac timing specifications as defined in figure 40 through figure 43 . input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in 0 v v in ov dd ?5 a table 54. jtag ac timing specifica tions (independent of sys_clk_in) 1 at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 033.3mhz? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 11 ? ns ? jtag external clock rise and fall times t jtgr , t jtgf 02ns? trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 2 2 15 15 ns 5 table 53. jtag interface dc electrical characteristics (continued) characteristic symbol condition min max unit
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 50 freescale semiconductor jtag the following figure provides the ac test load for tdo an d the boundary-scan outputs of the MPC8309. figure 39. ac test load for the jtag interface the following figure provides the jtag clock input timing diagram. figure 40. jtag clock input timing diagram the following figure provides the trst timing diagram. figure 41. trst timing diagram output hold times: boundary-scan data tdo t jtkldx t jtklox 2 2 ? ? ns 5 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 2 2 19 9 ns 5, 6 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are m easured at the pins. all output ti mings assume a purely resistive 50- load (see figure 39 ). time-of-flight delays must be added for trac e lengths, vias, and connectors in the system. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional . for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design and characterization. table 54. jtag ac timing specific ations (independen t of sys_clk_in) 1 (continued) at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 51 jtag the following figure provides the boundary-scan timing diagram. figure 42. boundary-scan timing diagram the following figure provides the test access port timing diagram. figure 43. test access port timing diagram vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid vm = midpoint voltage (ov dd /2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 52 freescale semiconductor package and pin listings 22 package and pin listings this section details package para meters, pin assignments, and dimens ions. the MPC8309 is available in a thermally enhanced mapbga (mold array process-ball grid array); see section 22.1, ?package parameters for the MPC8309,? and section 22.2, ?mechanical dimens ions of the MPC8309 mapbga,? for information on the mapbga. 22.1 package parameters for the mpc 8309 the package parameters are as provided in the following list. package outline 19 mm 19 mm package type mapbga interconnects 489 pitch 0.80 mm module height (typical) 1.48 mm; min = 1.31mm and max 1.61mm solder balls 96 sn / 3.5 ag / 0.5 cu (vm package) ball diameter (typical) 0.40 mm 22.2 mechanical dimensions of the MPC8309 mapbga the following figure shows the mechanical dime nsions and bottom surface nomenclature of the MPC8309, 489-mapbga package.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 53 package and pin listings figure 44. mechanical dimensions and bottom surface nomenclature of the MPC8309 mapbga notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 54 freescale semiconductor package and pin listings 22.3 pinout listings following table shows the pin list of the MPC8309. table 55. MPC8309 pinout listing signal terminal pad dir power supply notes ddr memory controller interface memc_mdq0 u5 io gv dd ? memc_mdq1 aa1 io gv dd ? memc_mdq2 w3 io gv dd ? memc_mdq3 r5 io gv dd ? memc_mdq4 w2 io gv dd ? memc_mdq5 u3 io gv dd ? memc_mdq6 u2 io gv dd ? memc_mdq7 t3 io gv dd ? memc_mdq8 h3 io gv dd ? memc_mdq9 h4 io gv dd ? memc_mdq10 g3 io gv dd ? memc_mdq11 f3 io gv dd ? memc_mdq12 g5 io gv dd ? memc_mdq13 f4 io gv dd ? memc_mdq14 f5 io gv dd ? memc_mdq15 e3 io gv dd ? memc_mdq16 v4 io gv dd ? memc_mdq17 y2 io gv dd ? memc_mdq18 y1 io gv dd ? memc_mdq19 u4 io gv dd ? memc_mdq20 v1 io gv dd ? memc_mdq21 r4 io gv dd ? memc_mdq22 u1 io gv dd ? memc_mdq23 t2 io gv dd ? memc_mdq24 j5 io gv dd ? memc_mdq25 g2 io gv dd ? memc_mdq26 g1 io gv dd ? memc_mdq27 f1 io gv dd ? memc_mdq28 e2 io gv dd ?
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 55 package and pin listings memc_mdq29 d2 io gv dd ? memc_mdq30 c2 io gv dd ? memc_mdq31 c1 io gv dd ? memc_mecc0 y5 io gv dd ? memc_mecc1 aa4 io gv dd ? memc_mecc2 y4 io gv dd ? memc_mecc3 aa3 io gv dd ? memc_mecc4 ac2 io gv dd ? memc_mecc5 ab2 io gv dd ? memc_mecc6 y3 io gv dd ? memc_mecc7 ab1 io gv dd ? memc_mdm0 w1 o gv dd ? memc_mdm1 e1 o gv dd ? memc_mdm2 v3 o gv dd ? memc_mdm3 d1 o gv dd ? memc_mdm8 w5 o gv dd ? memc_mdqs0 t5 io gv dd ? memc_mdqs1 h5 io gv dd ? memc_mdqs2 p5 io gv dd ? memc_mdqs3 e5 io gv dd - memc_mdqs8 v5 io gv dd - memc_mba0 k2 o gv dd - memc_mba1 k3 o gv dd - memc_mba2 n5 o gv dd - memc_ma0 l3 o gv dd - memc_ma1 l5 o gv dd - memc_ma2 l2 o gv dd - memc_ma3 l1 o gv dd - memc_ma4 m3 o gv dd - memc_ma5 m4 o gv dd - memc_ma6 m1 o gv dd - memc_ma7 n1 o gv dd - memc_ma8 n2 o gv dd - memc_ma9 n3 o gv dd - memc_ma10 l4 o gv dd - memc_ma11 p2 o gv dd - memc_ma12 n4 o gv dd -
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 56 freescale semiconductor package and pin listings memc_ma13 p1 o gv dd - memc_mwe_b j1 o gv dd - memc_mras_b k1 o gv dd - memc_mcas_b j3 o gv dd - memc_mcs_b0 j4 o gv dd - memc_mcs_b1 k5 o gv dd - memc_mcke p4 o gv dd - memc_mck0 r1 o gv dd - memc_mck1 r3 o gv dd - memc_mck_b0 t1 o gv dd - memc_mck_b1 p3 o gv dd - memc_modt0 h1 o gv dd - memc_modt1 h2 o gv dd - memc_mvref m6 gv dd - local bus controller interface lad0 b5 io ov dd - lad1 a4 io ov dd - lad2 c7 io ov dd - lad3 d9 io ov dd - lad4 a5 io ov dd - lad5 e10 io ov dd - lad6 a6 io ov dd - lad7 c8 io ov dd - lad8 d10 io ov dd - lad9 a7 io ov dd - lad10 b7 io ov dd - lad11 c9 io ov dd - lad12 e11 io ov dd - lad13 b8 io ov dd - lad14 a8 io ov dd - lad15 c10 io ov dd - la16 c11 io ov dd - la17 b10 o ov dd - la18 d12 o ov dd - la19 a9 o ov dd - la20 e12 o ov dd - la21 b11 o ov dd -
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 57 package and pin listings la22 a11 o ov dd - la23 a10 o ov dd - la24 c12 o ov dd - la25 a12 o ov dd - lclk0 e13 o ov dd - lcs_b0 d13 o ov dd 2 lcs_b1 c13 o ov dd 2 lcs_b2 a13 o ov dd 2 lcs_b3 b13 o ov dd 2 lwe_b0/lfwe_b0/lbs_b0 a14 o ov dd - lwe_b1/lbs_b1 b14 o ov dd - lbctl a15 o ov dd - lgpl0/lfcle c14 o ov dd - lgpl1/lfale c15 o ov dd - lgpl2/loe_b/lfre_b b16 o ov dd 2 lgpl3/lfwp_b a16 o ov dd - lgpl4/lgta_b/lupwait/lfrb_b e14 io ov dd 2 lgpl5 b17 o ov dd - lale a17 o ov dd - duart uart1_sout1 ab7 o ov dd - uart1_sin1 ac6 i ov dd - uart1_sout2/uart1_rts_b1 w10 o ov dd - uart1_sin2/uart1_cts_b1 y9 i ov dd - i2c iic_sda1 a20 io ov dd 1 iic_scl1 b20 io ov dd 1 iic_sda2 /ckstop_out_b d19 io ov dd 1 iic_scl2/ckstop_in_b c20 io ov dd 1 interrupts irq_b0_mcp_in_b a21 io ov dd - irq_b1/mcp_out_b a22 io ov dd - irq_b2/ckstop_in_b e18 i ov dd - irq_b3/ckstop_out_b/inta_b e19 io ov dd - spi spimosi b19 io ov dd -
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 58 freescale semiconductor package and pin listings spimiso e16 io ov dd - spiclk e17 io ov dd - spisel a19 i ov dd - spisel_boot_b d18 ov dd - jtag tck a2 i ov dd - tdi c5 i ov dd 2 tdo a3 o ov dd - tms d7 i ov dd 2 trst_b e9 i ov dd 2 test interface test_mode c6 i ov dd - system control signals hreset_b w23 io ov dd 1 poreset_b w22 i ov dd - clock interface qe_clk_in r22 i ov dd - sys_clk_in r23 i ov dd - sys_xtal_in p23 i ov dd - sys_xtal_out p19 o ov dd - pci_sync_in t23 i ov dd - pci_sync_out r20 o ov dd - cfg_clkin_div_b u23 i ov dd - rtc_pit_clock v23 i miscellaneous signals quiesce_b d6 o ov dd - therm0 e8 ov dd - gpio gpio_0/sd_clk/msrcid0 (ddr id) e4 io ov dd - gpio_1/sd_cmd/msrcid1 (ddr id) e6 io ov dd - gpio_2/sd_cd/msrcid2 (ddr id) d3 io ov dd - gpio_3/sd_wp/msrcid3 (ddr id) e7 io ov dd - gpio_4/sd_dat0/msrcid4 (ddr id) d4 io ov dd - gpio_5/sd_dat1/mdval (ddr id) c4 io ov dd - gpio_6/sd_dat2/qe_ext_req_3 b2 io ov dd - gpio_7/sd_dat3/qe_ext_req_1 b3 io ov dd - gpio_8/rxcan1/lsrcid0/lcs_b4 c16 io ov dd -
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 59 package and pin listings gpio_9/txcan1/lsrcid1/lcs_b5 c17 io ov dd - gpio_10/rxcan2/lsrcid2/lcs_b6 e15 io ov dd - gpio_11/txcan2/lsrcid3/lcs_b7 a18 io ov dd - gpio_12/rxcan3/lsrcid4/lclk1 d15 io ov dd - gpio_13/txcan3/ldval c18 io ov dd - gpio_14/rxcan4 d16 io ov dd - gpio_15/txcan4 c19 io ov dd - usb usbdr_pwrfault/ce_pio_1 aa6 i ov dd 1 usbdr_clk/uart2_sin2/uart2_cts_b1 ac9 i ov dd - usbdr_dir aa7 i ov dd - usbdr_nxt/uart2_sin1/qe_ext_req_4 ac5 i ov dd - usbdr_txdrxd0/gpio_32 y6 io ov dd - usbdr_txdrxd1/gpio_33 w9 io ov dd - usbdr_txdrxd2/gpio_34/qe_brg_1 ab5 io ov dd - usbdr_txdrxd3/gpio_35/qe_brg_2 aa5 io ov dd - usbdr_txdrxd4/gpio_36/qe_brg_3 y8 io ov dd - usbdr_txdrxd5/gpio_37/qe_brg_4 ac4 io ov dd - usbdr_txdrxd6/gpio_38/qe_brg_9 ac3 io ov dd - usbdr_txdrxd7/gpio_39/qe_brg_11 ab3 io ov dd - usbdr_pctl0/uart2_ sout1/lb_por_cfg _boot_ecc w8 o ov dd - usbdr_pctl1/uart2_ sout2/uart2_rts_b 1/lb_por_boot_err w7 o ov dd - usbdr_stp/qe_ext_req_2 w6 o ov dd - pci pci_inta_b b22 o ov dd - pci_reset_out_b f19 o ov dd - pci_ad0 b23 io ov dd - pci_ad1 c21 io ov dd - pci_ad2 e20 io ov dd - pci_ad3 g19 io ov dd - pci_ad4 c23 io ov dd - pci_ad5 h19 io ov dd - pci_ad6/ce_pio_0 d21 io ov dd - pci_ad7 f20 io ov dd -
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 60 freescale semiconductor package and pin listings pci_ad8/ e21 io ov dd - pci_ad9/ h20 io ov dd - pci_ad10/ d22 io ov dd - pci_ad11/ d23 io ov dd - pci_ad12/ j19 io ov dd - pci_ad13/ f21 io ov dd - pci_ad14/ g21 io ov dd - pci_ad15/ e22 io ov dd - pci_ad16/ e23 io ov dd - pci_ad17/ j20 io ov dd - pci_ad18/ f23 io ov dd - pci_ad19/ g23 io ov dd - pci_ad20 k19 io ov dd - pci_ad21 h21 io ov dd - pci_ad22 l19 io ov dd - pci_ad23 g22 io ov dd - pci_ad24 h23 io ov dd - pci_ad25 j21 io ov dd - pci_ad26 h22 io ov dd - pci_ad27 j23 io ov dd - pci_ad28 k18 io ov dd - pci_ad29 k21 io ov dd - pci_ad30 k22 io ov dd - pci_ad31 k23 io ov dd - pci_c_be_b0 l20 io ov dd - pci_c_be_b1 l23 io ov dd - pci_c_be_b2 l22 io ov dd - pci_c_be_b3 l21 io ov dd - pci_par m19 io ov dd - pci_frame_b m20 io ov dd - pci_trdy_b m23 io ov dd - pci_irdy_b m21 io ov dd - pci_stop_b n23 io ov dd - pci_devsel_b n22 io ov dd - pci_idsel n21 io ov dd - pci_serr_b n19 io ov dd - pci_perr_b p20 io ov dd -
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 61 package and pin listings pci_req_b0 p21 io ov dd - pci_req_b1/cpci_hs_es p22 io ov dd - pci_req_b2 t22 io ov dd - pci_gnt_b0 t21 io ov dd - pci_gnt_b1/cpci_hs_led u22 o ov dd - pci_gnt_b2/cpci_hs_enum u21 io ov dd - m66en v21 i ov dd - pci_clk0 t19 o ov dd - pci_clk1 u19 o ov dd - pci_clk2 r19 o ov dd - ethernet management fec_mdc w18 o ov dd - fec_mdio w17 io ov dd - fec/gtm/gpio fec1_col/gtm1_tin1/gpio_16 y18 io ov dd - fec1_crs/gtm1_tgate1_b/gpio_17 aa19 io ov dd - fec1_rx_clk[clk9]/gpio_18 w16 io ov dd - fec1_rx_dv/gtm1_tin2/gpio_19 ac22 io ov dd - fec1_rx_er/gtm1_tgate2_b/gpio_20 aa18 io ov dd - fec1_rxd0/gpio_21 ab20 io ov dd - fec1_rxd1/gtm1_tin3/gpio_22 y17 io ov dd - fec1_rxd2/gtm1_tgate3_b/gpio_23 ab19 io ov dd - fec1_rxd3/gpio_24 ac21 io ov dd - fec1_tx_clk[clk10]/gtm1_tin4/gpio_25 w15 io ov dd - fec1_tx_en/gtm1_tgat e4_b/gpio_26 ac19 io ov dd - fec1_tx_er/gtm1_tout4_b/gpio_27 ac20 io ov dd - fec1_txd0/gtm1_tout1_b/gpio_28/ aa17 io ov dd - fec1_txd1/gtm1_tout2_b/gpio_29 ac18 io ov dd - fec1_txd2/gtm1_tout3_b/gpio_30 aa16 io ov dd - fec1_txd3/gpio_31 ab17 io ov dd - fec2_col/gtm2_tin1/gpio_32 y15 io ov dd - fec2_crs/gtm2_tgate1_b/gpio_33 ac17 io ov dd -
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 62 freescale semiconductor package and pin listings fec2_rx_clk[clk7]/gpio_34 w14 io ov dd - fec2_rx_dv/gtm2_tin2/gpio_35 ab16 io ov dd - fec2_rx_er/gtm2_tgate2_b/gpio_36 y14 io ov dd - fec2_rxd0/gpio_37 aa15 io ov dd - fec2_rxd1/gtm2_tin3/gpio_38 ac15 io ov dd - fec2_rxd2/gtm2_tgate3_b/gpio_39 ac16 io ov dd - fec2_rxd3/gpio_40 aa14 io ov dd - fec2_tx_clk[clk8]/gtm2_ tin4/gpio_41 w13 io ov dd - fec2_tx_en/gtm2_tgat e4_b/gpio_42 ab14 io ov dd - fec2_tx_er/gtm2_tout4_b/gpio_43 ac14 io ov dd - fec2_txd0/gtm2_tout1_b/gpio_44 y12 io ov dd - fec2_txd1/gtm2_tout2_b/gpio_45 aa13 io ov dd - fec2_txd2/gtm2_tout3_b/gpio_46 ab13 io ov dd - fec2_txd3/gpio_47 ac13 io ov dd - fec3_col/gpio_48 ac12 io ov dd - fec3_crs/gpio_49 w11 io ov dd - fec3_rx_clk[clk11]/gpio_50 w12 io ov dd - fec3_rx_dv/fec1_tmr_tx _esfd/gpio_51 aa12 io ov dd - fec3_rx_er/fec1_tmr_rx_esfd/gpio_52 ab11 io ov dd - fec3_rxd0/fec2_tmr_t x_esfd/gpio_53 aa11 io ov dd - fec3_rxd1/fec2_tmr_rx_esfd/gpio_54 ac11 io ov dd - fec3_rxd2/fec_tmr_trig1/gpio_55 y11 io ov dd - fec3_rxd3/fec_tmr_trig2/gpio_56 ab10 io ov dd - fec3_tx_clk[clk12]/f ec_tmr_clk/gpio_5 7 ac10 io ov dd - fec3_tx_en/fec_tmr_g clk/gpio_58 aa10 io ov dd - fec3_tx_er/fec_tmr_ pp1/gpio_59 ac8 io ov dd - fec3_txd0/fec_tmr_pp2/gpio_60 ab8 io ov dd - fec3_txd1/fec_tmr_pp3/gpio_61 aa9 io ov dd - fec3_txd2/fec_tmr_alarm1/gpio_62 aa8 io ov dd - fec3_txd3/fec_tmr_alarm2/gpio_63 ac7 io ov dd -
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 63 package and pin listings hdlc/tdm/gpio hdlc1_txclk[clk16]/g pio_0/qe_brg_5/td m1_tck[clk4] aa20 io ov dd - hdlc1_rxclk[clk15]/gpio_1/tdm1_rck [clk3] aa21 io ov dd - hdlc1_txd/gpio_2/td m1_td/cfg_reset_ source[0] ab22 io ov dd 1 hdlc1_rxd/gpio_3/tdm1_rd ab23 io ov dd - hdlc1_cd_b/gpio_4/tdm1_tfs w19 io ov dd - hdlc1_cts_b/gpio_5/tdm1_rfs v19 io ov dd - hdlc1_rts_b/gpio_6/tdm1_strobe_b/cf g_reset_source[1] aa23 io ov dd - hdlc2_txclk[clk14]/gpio_16/qe_brg_7/t dm2_tck[clk6] y20 io ov dd - hdlc2_rxclk[clk13]/gpio_17/tdm2_rck [clk5]/qe_brg_8 y22 io ov dd - hdlc2_txd/gpio_18/tdm2_td/cfg_reset _source[2] w20 io ov dd 1 hdlc2_rxd/gpio_19/tdm2_rd w21 io ov dd - hdlc2_cd_b/gpio_20/tdm2_tfs v20 io ov dd - hdlc2_cts_b/gpio_21/tdm2_rfs y23 io ov dd - hdlc2_rts_b/gpio_22/tdm2_strobe_b/cf g_reset_source[3] u20 io ov dd - power avdd1 l16 - - - avdd2 m16 - - - avdd3 n8 - - - gvdd f6, g6, h6, j6, k6, l6, n6, p6, r6, t6, u6, v6, v7 --- nvdd f7, f8, f9, f10, f11, f12, f13,f14, f15, f16, f17, f18, g18,h18, j18, l18, m18, n18, p18,r18, t18, u18, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18 ---
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 64 freescale semiconductor package and pin listings vdd h8,h9,h10,h11,h12,m8, h13,n16,h14,h15,h16, p16,p8,l8,k16,j16,k8,j 8,r8,t16,r16,t8,t9,t11 ,t10,t12,t13,t14,t15 --- vss a1, c3, f22, j14, k14, m15, l15, n20, r9, y21, t20, ab21, b1, c22,g4, k15, j15, m2, m22, p9, r10, v2, aa2, ac1, b4,d5, g20, j22, k20, m5, n9, p10, r11, v22, aa22,ac23, b6, d8, j2, k4, m9,l9, n10, p11, r12, w4, ab4, d11, b9, j9, k9, l10,m10, n11, p12, r13, y7,ab6, b12, d14, j10, k10, l11, m11, p13, n12, r14, y10,ab9, b15, d17, j11, k11, d20, b18, j12, k12, l13, l12, l14, k13, j13, f2, b21, m14, m13, m12, y19, y16, ab15, ab12, y13, n13, n14, n15, p14, p15, r2, ab18, r15, r21, t4 --- nc a23 - - - notes 1. this pin is an open drain signal. a weak pull-up resistor should be placed on this pin to ov dd 2 this pin has weak pull-up that is always enabled. 4. ovdd here refers to nvdda, nvddb,nv ddc, nvddf, nvddg, and nvddh from the ball map.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 65 clocking 23 clocking the following figure shows the internal di stribution of clocks within the MPC8309. figure 45. MPC8309 clock subsystem the primary clock source for the MPC8309 can be one of three inputs,cr ystal(sys_xtal_in ), sys_clk_in or pci_sync_in, depe nding on whether the device is conf igured in pci host or pci agent mode, respectively. core pll system lbc lclk[0:1] core_clk e300c3 core csb_clk local bus clock unit of the device lbc_clk memory device /n clock memc_mck memc_mck ddr ddr_clk ddr memory device pll to ddr memory controller clock /2 divider divider qe pll clk gen qe block qe_clk qe_clk_in pci clock divider csb_clk to rest to local bus cfg_clkin_div pci_sync_out pci_clk[0:2] pci_sync_in /n MPC8309 rest of the system sys_xtal_out sys_xtal_in sys_clk_in crystal
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 66 freescale semiconductor clocking 23.1 clocking in pci host mode when the MPC8309 is configured as a pci host device (rcwh[pcihost] = 1), sys_clk_in is its primary input clock. sys_clk_in feeds the pci clock divider ( 2) and the pci_sync_out and pci_clk multiplexors. the cfg_clkin_div confi guration input selects wh ether sys_clk_in or sys_clk_in/2 is driven out on the pci_sync_out signal. pci_sync_out is connected externally to pci_sy nc_in to allow the internal clock subsystem to synchronize to the system pci clocks. pci_sync_out must be connected properly to pci_sync_in, with equal delay to all pci agent devices in the system. 23.1.1 pci clock outputs (pci_clk[0:2]) when the MPC8309 is configured as a pci host, it provides three separa te clock output signals, pci_clk[0:2], for external pci agents. when the device comes out of reset, the pci clock out puts are disabled and are ac tively driven to a steady low state. each of the individual clock outputs can be enabled (enable toggling of the cl ock) by setting its corresponding occr[pcicoe n ] bit. all output clocks are phase-aligned to each other. 23.2 clocking in pci agent mode when the MPC8309 is configured as a pci agent de vice, pci_sync_in is the primary input clock. in agent mode, the sys_clk_in signal should be tied to gnd, and the cloc k output signals, pci_clk n and pci_sync_out, are not used. 23.3 system clock domains as shown in figure 45 , the primary clock input (frequency) is multiplied up by the system phase-locked loop (pll) and the clock unit to create four majo r clock domains: ? the coherent system bus clock ( csb_clk ) ? the quicc engine clock ( qe_clk ) ? the internal clock for the ddr controller ( ddr_clk ) ? the internal clock for the local bus controller ( lbc_clk ) the csb_clk frequency is derived from the following equation: csb_clk = [pci_sync_in (1 + ~cfg_clkin_div )] spmf eqn. 1 in pci host mode, pci_sync_in = sys_clk_in (1 + ~ cfg_clkin_div ) . eqn. 2 the csb_clk serves as the clock input to the e300 core. a second pll inside the core multiplies up the csb_clk frequency to create the internal clock for the core ( core_clk ). the system and core pll multipliers are selected by the spmf and corepll fields in th e reset configuration word low (rcwl) which is loaded at power-on reset or by one of the hard-code d reset options. for more information, see the reset
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 67 clocking configuration chapter in the MPC8309 powerquicc ii pro integrated communications processor family reference manual . the qe_clk frequency is determined by the quicc engi ne pll multiplication factor (rcwl[cepmf]) and the quicc engine pll division factor (rcwl[cepdf]) as the following equation: qe_clk = (qe_clk_in cepmf) (1 + cepdf) eqn. 3 for more information, see the quicc engine pll mult iplication factor section and the ?quicc engine pll division factor? section in the MPC8309 powerquicc ii pro integrated communications processor family reference manual for more information. the ddr sdram memory controller operates with a frequency equal to twice the frequency of csb_clk . note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the ddr clock divider ( 2) to create the differential ddr me mory bus clock outputs (mck and mck ). however, the data rate is the same frequency as ddr_clk . the local bus memory controller operates wi th a frequency equal to the frequency of csb_clk . note that lbc_clk is not the external local bus frequency; lbc_clk passes through the lbc cloc k divider to create the external local bus clock outputs (lclk). the lbc clock divider ra tio is controlled by lcrr[clkdiv]. for more information, see the lbc bus clock and clock ratios section in the MPC8309 powerquicc ii pro integrated communications processor family reference manual . in addition, some of the internal uni ts may be required to be shut off or operate at lower frequency than the csb_clk frequency. these units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. the following table specifies which units have a conf igurable clock frequency. for detailed description, refer to the ?system clock control register (sccr)? section in the MPC8309 powerquicc ii pro integrated communications processor family reference manual . note setting the clock ratio of these units must be performed prior to any access to them. the following table provides th e maximum operating frequencie s for the MPC8309 mapbga under recommended operating conditions (see table 2 ). table 56. configurable clock units unit default frequency options i2c,sdhc, usb, dma complex csb_clk off, csb_clk, csb_clk /2, csb_clk /3 table 57. operating frequencies for mapbga characteristic 1 max operating frequency unit e300 core frequency ( core_clk )417mhz coherent system bus frequency ( csb_clk )167mhz quicc engine frequency ( qe_clk )233mhz
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 68 freescale semiconductor clocking 23.4 system pll configuration the system pll is controlled by the rcwl[spmf] parameter. table 58 shows the multiplication factor encodings for the system pll. note system pll vco frequency = 2 (csb frequency) (system pll vco divider). the vco divider needs to be set properly so that the system pll vco frequency is in the range of 450?750 mhz. as described in section 23, ?clocking,? the lbcm, ddrcm, and spmf parameters in the reset configuration word low select the ra tio between the primary clock input ( sys_clk_in) and the internal coherent system bus clock ( csb_clk ). the following table shows the expe cted frequency values for the csb frequency for selected csb_clk to sys_clk_in ratios. ddr2 memory bus frequency (mclk) 2 167 mhz local bus frequency (lclk n ) 3 66 mhz notes: 1. the sys_clk_in frequency, rcwl[spmf], and rcwl[corepll] settings must be chosen such that the resulting csb_clk, mclk, lclk, and core_clk frequencies do not e xceed their respective maximum or minimum operating frequencies. 2. the ddr2 data rate is 2 the ddr2 memory bus frequency. 3. the local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on lcrr[clkd iv]) which is in turn 1 or 2 the csb_clk frequency (depending on rcwl[lbcm]). table 58. system pll multiplication factors rcwl[spmf] system pll multiplication factor 0000 reserved 0001 reserved 0010 2 0011 3 0100 4 0101 5 0110 6 0111?1111 reserved table 57. operating frequencies for mapbga (continued) characteristic 1 max operating frequency unit
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 69 clocking 23.5 core pll configuration rcwl[corepll] selects the ratio between th e internal coherent system bus clock ( csb_clk ) and the e300 core clock ( core_clk ). the following table shows the en codings for rcwl[corepll]. corepll values not listed, and shoul d be considered reserved. table 59. csb frequency options spmf csb_clk : sys_clk_in ratio pci_sync_in(mhz) 25 33.33 66.67 csb_clk frequency (mhz) 0010 2:1 133 0011 3:1 0100 4:1 133 0101 5:1 125 167 0110 6:1 table 60. e300 core pll configuration rcwl[corepll] core_clk : csb_clk ratio vco divider 0-1 2-5 6 nn 0000 n pll bypassed (pll off, csb_clk clocks core directly) pll bypassed (pll off, csb_clk clocks core directly) 00 0001 0 1:1 2 01 0001 0 1:1 4 10 0001 0 1:1 8 11 0001 0 1:1 8 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 10 0001 1 1.5:1 8 11 0001 1 1.5:1 8 00 0010 0 2:1 2 01 0010 0 2:1 4 10 0010 0 2:1 8 11 0010 0 2:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 11 0010 1 2.5:1 8 00 0011 0 3:1 2
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 70 freescale semiconductor clocking note core vco frequency = core frequency vco divider. the vco divider (rcwl[corepll[0:1]]), mu st be set properly so that the core vco frequency is in the range of 400?800 mhz. 23.6 quicc engine pll configuration the quicc engine pll is controlled by the rc wl[cepmf] and rcwl[cepdf] parameters. the following table shows the multiplication f actor encodings for the quicc engine pll. the rcwl[cevcod] denotes the quicc engine p ll vco internal frequency as shown in the following table. 01 0011 0 3:1 4 10 0011 0 3:1 8 11 0011 0 3:1 8 table 61. quicc engine pll multiplication factors rcwl[cepmf] rcwl[cepdf] quicc engine pll multiplication factor = rcwl[cepmf]/ (1 + rcwl[cepdf) 00000?00001 0 reserved 00010 0 2 00011 0 3 00100 0 4 00101 0 5 00110 0 6 00111 0 7 01000 0 8 01001?11111 0 reserved table 62. quicc engine pll vco divider rcwl[cevcod] vco divider 00 2 01 4 10 8 11 reserved table 60. e300 core pll configuration (continued) rcwl[corepll] core_clk : csb_clk ratio vco divider 0-1 2-5 6
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 71 clocking note the vco divider (rcwl[cevcod]) must be set properly so that the quicc engine vco frequency is in the range of 300?600 mhz. the quicc engine frequency is not restrict ed by the csb and core frequencies. the csb, core, and quicc engine frequencies should be selected according to the performance requirements. the quicc engine vco frequency is derived from the following equations: qe_clk = (primary clock input cepmf) (1 + cepdf) quicc engine vco frequency = qe_clk vco divider (1 + cepdf) 23.7 suggested pll configurations to simplify the pll configurations, the MPC8309 might be separated into two clock domains. the first domain contains the csb pll and the core pll. the core pll is connected serially to the csb pll, and has the csb_clk as its input cloc k. the second clock domain has th e quicc engine pll. the clock domains are independent, and each of th eir plls is configured separately. the following table shows suggested pll conf igurations for 33 and 66 mhz input clocks. table 63. suggested pll configurations conf no. spmf core pll cepmf cedf input clock frequency (mhz) csb frequency (mhz) core frequency (mhz) quicc engine frequency (mhz) 1 0100 0000100 0111 0 33.33 133.33 266.66 233 2 0010 0000100 0111 1 66.67 133.33 266.66 233 3 0100 0000101 0111 0 33.33 133.33 333.33 233 4 0101 0000101 1001 0 25 125 312.5 225 5 0010 0000101 0111 1 66.67 133.33 333.33 233 6 0100 0000110 0111 0 33.33 133.33 399.96 233 7 0101 0000110 1000 0 25 125 375 225 8 0010 0000110 0011 0 66.67 133.33 399.96 233 9 0101 0000101 0111 0 33.33 166.67 416.67 233
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 72 freescale semiconductor thermal 24 thermal this section describes the therma l specifications of the MPC8309. 24.1 thermal characteristics the following table provides the packag e thermal characteristics for the 369, 19 19 mm mapbga of the MPC8309. 24.1.1 thermal management information for the following sections, p d =(v dd i dd )+p i/o , where p i/o is the power diss ipation of the i/o drivers. 24.1.2 estimation of junction temp erature with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , can be obtained from the equation: t j =t a +(r j a p d ) eqn. 1 where, t j = junction temperature ( c) table 64. package thermal characteristics for mapbga characteristic board type symbol value unit notes junction-to-ambient natural convection single-layer board (1s) r ja 40 c/w 1, 2 junction-to-ambient natural convection four-layer board (2s2p) r ja 25 c/w 1, 2, 3 junction-to-ambient (@200 ft/min) single-layer board (1s) r jma 33 c/w 1, 3 junction-to-ambient (@200 ft/min) four-layer board (2s2p) r jma 22 c/w 1, 3 junction-to-board ? r jb 15 c/w 4 junction-to-case ? r jc 9c/w5 junction-to-package top natural convection jt 2c/w6 notes: 1. junction temperature is a function of die size, on-chip powe r dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single layer board horizontal. board meets jesd51-9 specification. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, th e thermal characterization parameter is written as psi-jt.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 73 thermal t a = ambient temperature for the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an i ndustry standard value that provides a quick and easy estimation of thermal performance. as a general statement, the value obtained on a single layer board is appropriate for a tightly packed pr inted-circuit board. the value obtained on the board with the internal planes is usually appropriate if th e board has low power diss ipation and the component s are well separated. test cases have demonstrated that erro rs of a factor of two (in the quantity t j ? t a ) are possible. 24.1.3 estimation of junction temper ature with junction-to-board thermal resistance the thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. the thermal performan ce of any component is strongly de pendent on the power dissipation of surrounding components. in addition, the ambient temperature varies wi dely within the application. for many natural convection and especial ly closed box applications, the boa rd temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determ ine the temperature of the device. at a known board temperature, th e junction temperature is estima ted using the following equation: t j =t b +(r j b p d ) eqn. 2 where, t j = junction temperature ( c) t b = board temperature at the package perimeter ( c) r jb = junction-to-board thermal resistance ( c/w) per jesd51-8 p d = power dissipation in package (w) when the heat loss from the package case to the ai r can be ignored, acceptable predictions of junction temperature can be made. the appli cation board should be similar to the thermal test condition: the component is soldered to a board with internal planes. 24.1.4 experimental determinat ion of junction temperature to determine the junction temperatur e of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j =t t +( jt p d ) eqn. 3 where, t j = junction temperature ( c)
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 74 freescale semiconductor thermal t t = thermocouple temperature on top of package ( c) jt = thermal characterization parameter ( c/w) p d = power dissipation in package (w) the thermal characterization parame ter is measured per jesd51-2 spec ification using a 40 gauge type t thermocouple epoxied to the top center of the pack age case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from th e junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 24.1.5 heat sinks and juncti on-to-case thermal resistance in some application envir onments, a heat sink is required to provide the necessary thermal management of the device. when a heat sink is used, the thermal resi stance is expressed as the sum of a junction-to-case thermal resistance and a case to ambient thermal resistance as shown in the following equation: r ja =r jc +r ca eqn. 4 where: r ja = junction-to-ambient thermal resistance ( c/w) r jc = junction-to-case thermal resistance ( c/w) r ca = case-to-ambient thermal resistance ( c/w) r jc is device related and cannot be in fluenced by the user. the user cont rols the thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can ch ange the size of the heat sink, the air flow around the device, the interface material, the mounti ng arrangement on printed-circuit board, or change the thermal dissipation on th e printed-circuit board surrounding the device. to illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. the heat sink choice is determined by the application environment (temperature, air flow, ad jacent component power dissipation) and the physical space available. because there is not a standard appl ication environment, a standard heat sink is not required. accurate thermal design requires thermal modeling of the application environm ent using computational fluid dynamics software which can model both the conduction cooling a nd the convection cooling of the air moving through the application. si mplified thermal models of the pa ckages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in th e thermal resistance table. more detailed thermal models can be made available on request. 24.2 heat sink attachment when attaching heat sinks to these devices, an inte rface material is required. the best method is to use thermal grease and a spring clip. the spring clip should connect to the pr inted-circuit board, either to the board itself, to hooks soldered to th e board, or to a plastic stiffener. avoid attachment fo rces which would lift the edge of the package or peel the package from the board. such peeling forc es reduce the solder joint
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 75 system design information lifetime of the package. recommende d maximum force on the top of the p ackage is 10 lb (4.5 kg) force. if an adhesive attachment is planne d, the adhesive should be intended fo r attachment to painted or plastic surfaces and its performa nce verified under the a pplication requirements. 24.2.1 experimental determination of th e junction temperature with a heat sink when heat sink is used, the juncti on temperature is determined from a thermocouple inserted at the interface between the case of the package and the in terface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many e ngineers measure the heat sink temperature and then back calculate the case temperature using a separa te measurement of the thermal resistance of the interface. from this case temperature, the junction temperatur e is determined from the junction-to-case thermal resistance using the following equation: t j = t c +( r jc p d ) eqn. 5 where: t c = case temperature of the package ( c) r jc = junction-to-case thermal resistance ( c/w) p d = power dissipation (w) 25 system design information this section provides elect rical and thermal design r ecommendations for successf ul application of the MPC8309. 25.1 system clocking the MPC8309 includes three plls. ? the system pll (av dd2 ) generates the system clock from th e externally supplied sys_clk_in input. the frequency ratio between the system and sys_clk_in is selected using the system pll ratio configuration bits as described in section 23.4, ?system pll configuration.? ? the e300 core pll (av dd3 ) generates the core clock as a slave to the system clock. the frequency ratio between the e300 core clock and the system clock is selected using the e300 pll ratio configuration bits as described in section 23.5, ?core pll configuration.? ? the quicc engine pll (av dd1 ) which uses the same reference as the system pll. the quicc engine block generates or uses external sour ces for all required serial interface clocks.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 76 freescale semiconductor system design information 25.2 pll power supply filtering each of the plls listed above is provided with power through inde pendent power supply pins. the voltage level at each av dd n pin should always be equivalent to v dd , and preferably thes e voltages are derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to relia bly provide power to the plls, but the recommended solution is to provide independent filter ci rcuits as illustrated in figure 46 , one to each of the three av dd pins. by providing independent filters to eac h pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacito rs with minimum effective series inductance (esl). consistent with the recommenda tions of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as close as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route direct ly from the capacitors to the av dd pin, which is on the periphery of pack age, without the inductance of vias. the following figure shows the pll power supply filter circuit. figure 46. pll power supply filter circuit 25.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the MPC8309 can generate transient power surges and high freque ncy noise in its power suppl y, especially while drivi ng large capacitive loads. this noise must be prevented from reaching ot her components in the MPC8309 system, and MPC8309 itself requires a clean, tightly regul ated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , ov dd , and gv dd pins of the MPC8309. these decoupling capacitors should receive their power from separate v dd , ov dd , gv dd , and gnd power planes in the pcb, utilizing short traces to minimize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a va lue of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be severa l bulk storage capacitors distributed around the pcb, feeding the v dd , ov dd , and gv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent se ries resistance) rating to ensure the quick response time necessary. they shoul d also be connected to the power and ground planes through two vias v dd av dd 2.2 f 2.2 f gnd low esl surface mount capacitors (<0.5 nh) 10
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 77 system design information to minimize inductance. suggested bulk capa citors?100 to 330 f (avx tps tantalum or sanyo oscon). 25.4 output buffer dc impedance for all buses, the driver is a push-pull si ngle-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external re sistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until th e pad voltage is ov dd /2 (see figure 47 ). the output impedance is the av erage of two components, the resistances of the pul l-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistan ce of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 =(r p +r n )/2. figure 47. driver impedance measurement the value of this resistance and the strength of the driver?s current source can be found by making two measurements. first, the out put voltage is measured while driving l ogic 1 without an exte rnal differential termination resistor. the measured voltage is v 1 = r source i source . second, the output voltage is measured while driving logic 1 with an external precisi on differential termination resistor of value r term . the measured voltage is v 2 =(1/(1/r 1 +1/r 2 )) i source . solving for the output impedance gives r source =r term (v 1 /v 2 ? 1). the drive current is then i source =v 1 /r source . ov dd ognd r p r n pad data sw1 sw2
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 78 freescale semiconductor ordering information the following table summarizes th e signal impedance targets. the dr iver impedance is targeted at minimum v dd , nominal ov dd , 105 c. 25.5 configuration pin multiplexing the MPC8309 provides the user with power-on configuration options wh ich can be set th rough the use of external pull-up or pull- down resistors of 4.7 k on certain output pins (refer to the ?reset, clocking and initialization? of MPC8309 powerquicc ii pro integrated communications processor family reference manual ). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time th e input receiver is disabled and the i/o circuit takes on its nor mal function. careful board layout w ith stubless connections to these pull-up/pull-down resistors coupled wi th the large value of the pull-up/ pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. 26 ordering information this section presents ordering information for the de vices discussed in this document, and it shows an example of how the parts are marke d. ordering information for the devi ces fully covered by this document is provided in section 26.1, ?part numbers fully addressed by this document.? 26.1 part numbers fully addressed by this document the following table provides the freescale part num bering nomenclature for the MPC8309 family. note that the individual part numbers correspond to a ma ximum processor core frequency. for available frequencies, contact your local fr eescale sales office. in addition to the maximum processor core frequency, the part numbering scheme also incl udes the maximum effective ddr memory speed and quicc engine bus frequency. each pa rt number also contains a revision c ode which refers to the die mask revision number. table 65. impedance characteristics impedance local bus, ethernet, duart, control, configuration and power management ddr dram symbol unit r n 42 target 20 target z 0 r p 42 target 20 target z 0 differential na na z diff note: nominal supply voltages. see ta bl e 1 , t j = 105 c.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 freescale semiconductor 79 ordering information 26.2 part marking parts are marked as in the exampl e shown in the following figure. figure 48. freescale part marking for mapbga devices the following table shows the svr settings. table 66. part numbering nomenclature mpc nnnn c vm af d c a product code part identifier temperature range 1 package 2 e300 core frequency 3 ddr2 frequency quicc engine frequency revision level mpc 8309 blank = 0 to 105 c c = ?40 to 105 c vm = pb-free ad = 266 mhz af = 333 mhz ag = 400 mhz ah = 417mhz d = 266 mhz f = 333 mhz c = 233 mhz contact local freescale sales office notes: 1. contact local freescale office on availability of parts with c temperature range. 2. see section 22, ?package and pin listings,? for more information on available package types. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies. table 67. svr settings device package svr (rev 1.0) svr (rev 1.1) MPC8309 mapbga 0x8110_0010 0x8110_0011 note: pvr = 0x8085_0020 mpcnnnnetppaaar core/platform mhz at w ly y w w ccccc mapbga *mmmmm ywwlaz notes : atwlyyww is the traceability code. ccccc is the country code. mmmmm is the mask number. ywwlaz is the assembly traceability code.
MPC8309 powerquicc ii pro integrated communications processor family hardware specifications, rev. 3 80 freescale semiconductor document revision history 27 document revision history the following table provides a re vision history for this document. table 68. document revision history rev. no. date substantive change(s) 3 04/2014 ? re-introduced section 8.3.3, ?ieee 158 8 dc specifications and section 8.3.4, ?ieee 1588 ac specifications 2 09/2012 ? in ta b l e 5 5 , swapped clk13 and clk14. ?in ta b l e 5 5 , removed the following test signals, as there are no corresponding use cases: ? ecid_tmode_in ? boot_rom_addr[2] to boot_rom_addr[12] ? boot_rom_rdata[0] to boot_rom_rdata[31] ? boot_rom_mod_en, boot_rom_rwb, bo ot_rom_xfr_wait, boot_rom_xfr_err ? uc1_rm, uc2_rm, uc3_rm, uc5_rm, uc7_rm, and urm_trig ? tpr_sys_aad[0] to tpr_sys_aad[15] ? tpr_sys_sync, tpr_sys_dack ? qe_trb_0, qe_trb_1 ? pllcz_core_clkin ? jtag_bise, jtag_prpgps, jtag_bisr_tdo_en ? clock_xlb_clock_out ? pd_xlb2mg_ddr_clock ?in ta bl e 5 5 , changed the following signal names as only qe-based fast ethernet controller is present in this device: ? tsec_tmr_trig1 to fec_tmr_trig1 ? tsec_tmr_trig2 to fec_tmr_trig2 ? tsec_tmr_clk to fec_tmr_clk ? tsec_tmr_gclk to fec_tmr_gclk ? tsec_tmr_pp1 to fec_tmr_pp1 ? tsec_tmr_pp2 to fec_tmr_pp2 ? tsec_tmr_pp3 to fec_tmr_pp3 ? tsec_tmr_alarm1 to fec_tmr_alarm1 ? tsec_tmr_alarm2 to fec_tmr_alarm2 ? fec3_tmr_tx_esfd to fec2_tmr_tx_esfd ? fec3_tmr_rx_esfd to fec2_tmr_rx_esfd. ?in ta bl e 1 8 , added parameteres t lalehov ,, t laletot , and t lbotot and made the corresponding updates in figure 8 ?in figure 3 , replaced "32 x tsys_ clk_in" with "32 x t sys_clk_in/pci_sync_in. 1 08/2011 ? updated quicc engine frequency in ta bl e 5 . ? updated quicc engine frequency from 200 mhz to 233 mhz in ta b l e 6 3 . ? updated cepmf and cedf as per new qe frequency in ta b l e 6 3 . ? updated quicc engine frequency to 233 mhz in ta b l e 6 6 . ? corrected lccr to lcrr for all instances. 0 03/2011 initial release.
document number: MPC8309ec rev. 3 04/2014 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabr icate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any produc t or circuit, and specifically disclaims any and all liability, including wit hout limitation consequent ial or incidental damages. ?typical? parameters which may be provided in freescale data sheets and/or specifications can and do vary in differen t applications, and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the right s of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions freescale, the freescale logo, and powerquicc are trademarks of freescale semiconductor, inc. reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2011, 2012, 2014 freescale semiconductor, inc. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support

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